target: Clean up how the dump_mmu() print
The various dump_mmu() take an fprintf()-like callback and a FILE * to pass to it, and so do their helper functions. Passing around callback and argument is rather tiresome. Most dump_mmu() are called only by the target's hmp_info_tlb(). These all pass monitor_printf() cast to fprintf_function and the current monitor cast to FILE *. SPARC's dump_mmu() gets also called from target/sparc/ldst_helper.c a few times #ifdef DEBUG_MMU. These calls pass fprintf() and stdout. The type-punning is technically undefined behaviour, but works in practice. Clean up: drop the callback, and call qemu_printf() instead. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <20190417191805.28198-11-armbru@redhat.com>
This commit is contained in:
parent
0442428a89
commit
fad866daa8
@ -573,5 +573,6 @@ static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc,
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}
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}
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}
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}
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void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUM68KState *env);
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void dump_mmu(CPUM68KState *env);
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#endif
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#endif
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@ -369,30 +369,28 @@ int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
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/* MMU: 68040 only */
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/* MMU: 68040 only */
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static void print_address_zone(FILE *f, fprintf_function cpu_fprintf,
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static void print_address_zone(uint32_t logical, uint32_t physical,
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uint32_t logical, uint32_t physical,
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uint32_t size, int attr)
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uint32_t size, int attr)
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{
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{
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cpu_fprintf(f, "%08x - %08x -> %08x - %08x %c ",
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qemu_printf("%08x - %08x -> %08x - %08x %c ",
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logical, logical + size - 1,
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logical, logical + size - 1,
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physical, physical + size - 1,
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physical, physical + size - 1,
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attr & 4 ? 'W' : '-');
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attr & 4 ? 'W' : '-');
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size >>= 10;
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size >>= 10;
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if (size < 1024) {
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if (size < 1024) {
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cpu_fprintf(f, "(%d KiB)\n", size);
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qemu_printf("(%d KiB)\n", size);
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} else {
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} else {
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size >>= 10;
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size >>= 10;
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if (size < 1024) {
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if (size < 1024) {
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cpu_fprintf(f, "(%d MiB)\n", size);
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qemu_printf("(%d MiB)\n", size);
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} else {
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} else {
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size >>= 10;
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size >>= 10;
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cpu_fprintf(f, "(%d GiB)\n", size);
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qemu_printf("(%d GiB)\n", size);
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}
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}
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}
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}
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}
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}
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static void dump_address_map(FILE *f, fprintf_function cpu_fprintf,
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static void dump_address_map(CPUM68KState *env, uint32_t root_pointer)
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CPUM68KState *env, uint32_t root_pointer)
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{
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{
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int i, j, k;
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int i, j, k;
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int tic_size, tic_shift;
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int tic_size, tic_shift;
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@ -454,7 +452,7 @@ static void dump_address_map(FILE *f, fprintf_function cpu_fprintf,
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if (first_logical != 0xffffffff) {
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if (first_logical != 0xffffffff) {
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size = last_logical + (1 << tic_shift) -
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size = last_logical + (1 << tic_shift) -
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first_logical;
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first_logical;
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print_address_zone(f, cpu_fprintf, first_logical,
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print_address_zone(first_logical,
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first_physical, size, last_attr);
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first_physical, size, last_attr);
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}
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}
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first_logical = logical;
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first_logical = logical;
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@ -465,126 +463,125 @@ static void dump_address_map(FILE *f, fprintf_function cpu_fprintf,
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}
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}
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if (first_logical != logical || (attr & 4) != (last_attr & 4)) {
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if (first_logical != logical || (attr & 4) != (last_attr & 4)) {
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size = logical + (1 << tic_shift) - first_logical;
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size = logical + (1 << tic_shift) - first_logical;
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print_address_zone(f, cpu_fprintf, first_logical, first_physical, size,
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print_address_zone(first_logical, first_physical, size, last_attr);
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last_attr);
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}
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}
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}
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}
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#define DUMP_CACHEFLAGS(a) \
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#define DUMP_CACHEFLAGS(a) \
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switch (a & M68K_DESC_CACHEMODE) { \
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switch (a & M68K_DESC_CACHEMODE) { \
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case M68K_DESC_CM_WRTHRU: /* cachable, write-through */ \
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case M68K_DESC_CM_WRTHRU: /* cachable, write-through */ \
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cpu_fprintf(f, "T"); \
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qemu_printf("T"); \
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break; \
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break; \
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case M68K_DESC_CM_COPYBK: /* cachable, copyback */ \
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case M68K_DESC_CM_COPYBK: /* cachable, copyback */ \
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cpu_fprintf(f, "C"); \
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qemu_printf("C"); \
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break; \
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break; \
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case M68K_DESC_CM_SERIAL: /* noncachable, serialized */ \
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case M68K_DESC_CM_SERIAL: /* noncachable, serialized */ \
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cpu_fprintf(f, "S"); \
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qemu_printf("S"); \
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break; \
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break; \
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case M68K_DESC_CM_NCACHE: /* noncachable */ \
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case M68K_DESC_CM_NCACHE: /* noncachable */ \
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cpu_fprintf(f, "N"); \
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qemu_printf("N"); \
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break; \
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break; \
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}
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}
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static void dump_ttr(FILE *f, fprintf_function cpu_fprintf, uint32_t ttr)
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static void dump_ttr(uint32_t ttr)
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{
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{
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if ((ttr & M68K_TTR_ENABLED) == 0) {
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if ((ttr & M68K_TTR_ENABLED) == 0) {
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cpu_fprintf(f, "disabled\n");
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qemu_printf("disabled\n");
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return;
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return;
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}
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}
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cpu_fprintf(f, "Base: 0x%08x Mask: 0x%08x Control: ",
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qemu_printf("Base: 0x%08x Mask: 0x%08x Control: ",
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ttr & M68K_TTR_ADDR_BASE,
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ttr & M68K_TTR_ADDR_BASE,
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(ttr & M68K_TTR_ADDR_MASK) << M68K_TTR_ADDR_MASK_SHIFT);
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(ttr & M68K_TTR_ADDR_MASK) << M68K_TTR_ADDR_MASK_SHIFT);
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switch (ttr & M68K_TTR_SFIELD) {
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switch (ttr & M68K_TTR_SFIELD) {
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case M68K_TTR_SFIELD_USER:
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case M68K_TTR_SFIELD_USER:
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cpu_fprintf(f, "U");
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qemu_printf("U");
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break;
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break;
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case M68K_TTR_SFIELD_SUPER:
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case M68K_TTR_SFIELD_SUPER:
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cpu_fprintf(f, "S");
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qemu_printf("S");
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break;
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break;
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default:
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default:
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cpu_fprintf(f, "*");
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qemu_printf("*");
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break;
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break;
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}
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}
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DUMP_CACHEFLAGS(ttr);
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DUMP_CACHEFLAGS(ttr);
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if (ttr & M68K_DESC_WRITEPROT) {
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if (ttr & M68K_DESC_WRITEPROT) {
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cpu_fprintf(f, "R");
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qemu_printf("R");
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} else {
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} else {
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cpu_fprintf(f, "W");
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qemu_printf("W");
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}
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}
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cpu_fprintf(f, " U: %d\n", (ttr & M68K_DESC_USERATTR) >>
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qemu_printf(" U: %d\n", (ttr & M68K_DESC_USERATTR) >>
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M68K_DESC_USERATTR_SHIFT);
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M68K_DESC_USERATTR_SHIFT);
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}
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}
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void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUM68KState *env)
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void dump_mmu(CPUM68KState *env)
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{
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{
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if ((env->mmu.tcr & M68K_TCR_ENABLED) == 0) {
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if ((env->mmu.tcr & M68K_TCR_ENABLED) == 0) {
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cpu_fprintf(f, "Translation disabled\n");
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qemu_printf("Translation disabled\n");
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return;
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return;
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}
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}
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cpu_fprintf(f, "Page Size: ");
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qemu_printf("Page Size: ");
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if (env->mmu.tcr & M68K_TCR_PAGE_8K) {
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if (env->mmu.tcr & M68K_TCR_PAGE_8K) {
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cpu_fprintf(f, "8kB\n");
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qemu_printf("8kB\n");
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} else {
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} else {
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cpu_fprintf(f, "4kB\n");
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qemu_printf("4kB\n");
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}
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}
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cpu_fprintf(f, "MMUSR: ");
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qemu_printf("MMUSR: ");
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if (env->mmu.mmusr & M68K_MMU_B_040) {
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if (env->mmu.mmusr & M68K_MMU_B_040) {
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cpu_fprintf(f, "BUS ERROR\n");
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qemu_printf("BUS ERROR\n");
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} else {
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} else {
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cpu_fprintf(f, "Phy=%08x Flags: ", env->mmu.mmusr & 0xfffff000);
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qemu_printf("Phy=%08x Flags: ", env->mmu.mmusr & 0xfffff000);
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/* flags found on the page descriptor */
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/* flags found on the page descriptor */
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if (env->mmu.mmusr & M68K_MMU_G_040) {
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if (env->mmu.mmusr & M68K_MMU_G_040) {
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cpu_fprintf(f, "G"); /* Global */
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qemu_printf("G"); /* Global */
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} else {
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} else {
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cpu_fprintf(f, ".");
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qemu_printf(".");
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}
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}
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if (env->mmu.mmusr & M68K_MMU_S_040) {
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if (env->mmu.mmusr & M68K_MMU_S_040) {
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cpu_fprintf(f, "S"); /* Supervisor */
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qemu_printf("S"); /* Supervisor */
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} else {
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} else {
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cpu_fprintf(f, ".");
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qemu_printf(".");
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}
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}
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if (env->mmu.mmusr & M68K_MMU_M_040) {
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if (env->mmu.mmusr & M68K_MMU_M_040) {
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cpu_fprintf(f, "M"); /* Modified */
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qemu_printf("M"); /* Modified */
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} else {
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} else {
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cpu_fprintf(f, ".");
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qemu_printf(".");
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}
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}
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if (env->mmu.mmusr & M68K_MMU_WP_040) {
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if (env->mmu.mmusr & M68K_MMU_WP_040) {
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cpu_fprintf(f, "W"); /* Write protect */
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qemu_printf("W"); /* Write protect */
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} else {
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} else {
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cpu_fprintf(f, ".");
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qemu_printf(".");
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}
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}
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if (env->mmu.mmusr & M68K_MMU_T_040) {
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if (env->mmu.mmusr & M68K_MMU_T_040) {
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cpu_fprintf(f, "T"); /* Transparent */
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qemu_printf("T"); /* Transparent */
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} else {
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} else {
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cpu_fprintf(f, ".");
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qemu_printf(".");
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}
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}
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if (env->mmu.mmusr & M68K_MMU_R_040) {
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if (env->mmu.mmusr & M68K_MMU_R_040) {
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cpu_fprintf(f, "R"); /* Resident */
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qemu_printf("R"); /* Resident */
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} else {
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} else {
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cpu_fprintf(f, ".");
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qemu_printf(".");
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}
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}
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cpu_fprintf(f, " Cache: ");
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qemu_printf(" Cache: ");
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DUMP_CACHEFLAGS(env->mmu.mmusr);
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DUMP_CACHEFLAGS(env->mmu.mmusr);
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cpu_fprintf(f, " U: %d\n", (env->mmu.mmusr >> 8) & 3);
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qemu_printf(" U: %d\n", (env->mmu.mmusr >> 8) & 3);
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cpu_fprintf(f, "\n");
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qemu_printf("\n");
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}
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}
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cpu_fprintf(f, "ITTR0: ");
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qemu_printf("ITTR0: ");
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dump_ttr(f, cpu_fprintf, env->mmu.ttr[M68K_ITTR0]);
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dump_ttr(env->mmu.ttr[M68K_ITTR0]);
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cpu_fprintf(f, "ITTR1: ");
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qemu_printf("ITTR1: ");
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dump_ttr(f, cpu_fprintf, env->mmu.ttr[M68K_ITTR1]);
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dump_ttr(env->mmu.ttr[M68K_ITTR1]);
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cpu_fprintf(f, "DTTR0: ");
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qemu_printf("DTTR0: ");
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dump_ttr(f, cpu_fprintf, env->mmu.ttr[M68K_DTTR0]);
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dump_ttr(env->mmu.ttr[M68K_DTTR0]);
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cpu_fprintf(f, "DTTR1: ");
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qemu_printf("DTTR1: ");
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dump_ttr(f, cpu_fprintf, env->mmu.ttr[M68K_DTTR1]);
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dump_ttr(env->mmu.ttr[M68K_DTTR1]);
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cpu_fprintf(f, "SRP: 0x%08x\n", env->mmu.srp);
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qemu_printf("SRP: 0x%08x\n", env->mmu.srp);
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dump_address_map(f, cpu_fprintf, env, env->mmu.srp);
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dump_address_map(env, env->mmu.srp);
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cpu_fprintf(f, "URP: 0x%08x\n", env->mmu.urp);
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qemu_printf("URP: 0x%08x\n", env->mmu.urp);
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dump_address_map(f, cpu_fprintf, env, env->mmu.urp);
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dump_address_map(env, env->mmu.urp);
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}
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}
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static int check_TTR(uint32_t ttr, int *prot, target_ulong addr,
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static int check_TTR(uint32_t ttr, int *prot, target_ulong addr,
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@ -19,7 +19,7 @@ void hmp_info_tlb(Monitor *mon, const QDict *qdict)
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return;
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return;
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}
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}
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dump_mmu((FILE *)mon, (fprintf_function)monitor_printf, env1);
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dump_mmu(env1);
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}
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}
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static const MonitorDef monitor_defs[] = {
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static const MonitorDef monitor_defs[] = {
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@ -212,7 +212,7 @@ static inline Nios2CPU *nios2_env_get_cpu(CPUNios2State *env)
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void nios2_tcg_init(void);
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void nios2_tcg_init(void);
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void nios2_cpu_do_interrupt(CPUState *cs);
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void nios2_cpu_do_interrupt(CPUState *cs);
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int cpu_nios2_signal_handler(int host_signum, void *pinfo, void *puc);
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int cpu_nios2_signal_handler(int host_signum, void *pinfo, void *puc);
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void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUNios2State *env);
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void dump_mmu(CPUNios2State *env);
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void nios2_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
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void nios2_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
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int flags);
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int flags);
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hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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@ -20,6 +20,7 @@
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#include "qemu/osdep.h"
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "qemu-common.h"
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#include "qemu/qemu-print.h"
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#include "cpu.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "exec/exec-all.h"
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#include "mmu.h"
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#include "mmu.h"
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@ -264,18 +265,18 @@ void mmu_init(CPUNios2State *env)
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mmu->tlb = g_new0(Nios2TLBEntry, cpu->tlb_num_entries);
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mmu->tlb = g_new0(Nios2TLBEntry, cpu->tlb_num_entries);
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}
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}
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void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUNios2State *env)
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void dump_mmu(CPUNios2State *env)
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{
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{
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Nios2CPU *cpu = nios2_env_get_cpu(env);
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Nios2CPU *cpu = nios2_env_get_cpu(env);
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int i;
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int i;
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cpu_fprintf(f, "MMU: ways %d, entries %d, pid bits %d\n",
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qemu_printf("MMU: ways %d, entries %d, pid bits %d\n",
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cpu->tlb_num_ways, cpu->tlb_num_entries,
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cpu->tlb_num_ways, cpu->tlb_num_entries,
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cpu->pid_num_bits);
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cpu->pid_num_bits);
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for (i = 0; i < cpu->tlb_num_entries; i++) {
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for (i = 0; i < cpu->tlb_num_entries; i++) {
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Nios2TLBEntry *entry = &env->mmu.tlb[i];
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Nios2TLBEntry *entry = &env->mmu.tlb[i];
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cpu_fprintf(f, "TLB[%d] = %08X %08X %c VPN %05X "
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qemu_printf("TLB[%d] = %08X %08X %c VPN %05X "
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"PID %02X %c PFN %05X %c%c%c%c\n",
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"PID %02X %c PFN %05X %c%c%c%c\n",
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i, entry->tag, entry->data,
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i, entry->tag, entry->data,
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(entry->tag & (1 << 10)) ? 'V' : '-',
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(entry->tag & (1 << 10)) ? 'V' : '-',
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@ -31,5 +31,5 @@ void hmp_info_tlb(Monitor *mon, const QDict *qdict)
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{
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{
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CPUArchState *env1 = mon_get_cpu_env();
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CPUArchState *env1 = mon_get_cpu_env();
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dump_mmu((FILE *)mon, (fprintf_function)monitor_printf, env1);
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dump_mmu(env1);
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}
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}
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@ -2629,7 +2629,7 @@ static inline ppc_avr_t *cpu_avr_ptr(CPUPPCState *env, int i)
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return (ppc_avr_t *)((uintptr_t)env + avr_full_offset(i));
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return (ppc_avr_t *)((uintptr_t)env + avr_full_offset(i));
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}
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}
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void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
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void dump_mmu(CPUPPCState *env);
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|
|
||||||
void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
|
void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
|
||||||
#endif /* PPC_CPU_H */
|
#endif /* PPC_CPU_H */
|
||||||
|
@ -22,6 +22,7 @@
|
|||||||
#include "exec/exec-all.h"
|
#include "exec/exec-all.h"
|
||||||
#include "exec/helper-proto.h"
|
#include "exec/helper-proto.h"
|
||||||
#include "qemu/error-report.h"
|
#include "qemu/error-report.h"
|
||||||
|
#include "qemu/qemu-print.h"
|
||||||
#include "sysemu/hw_accel.h"
|
#include "sysemu/hw_accel.h"
|
||||||
#include "kvm_ppc.h"
|
#include "kvm_ppc.h"
|
||||||
#include "mmu-hash64.h"
|
#include "mmu-hash64.h"
|
||||||
@ -71,7 +72,7 @@ static ppc_slb_t *slb_lookup(PowerPCCPU *cpu, target_ulong eaddr)
|
|||||||
return NULL;
|
return NULL;
|
||||||
}
|
}
|
||||||
|
|
||||||
void dump_slb(FILE *f, fprintf_function cpu_fprintf, PowerPCCPU *cpu)
|
void dump_slb(PowerPCCPU *cpu)
|
||||||
{
|
{
|
||||||
CPUPPCState *env = &cpu->env;
|
CPUPPCState *env = &cpu->env;
|
||||||
int i;
|
int i;
|
||||||
@ -79,14 +80,14 @@ void dump_slb(FILE *f, fprintf_function cpu_fprintf, PowerPCCPU *cpu)
|
|||||||
|
|
||||||
cpu_synchronize_state(CPU(cpu));
|
cpu_synchronize_state(CPU(cpu));
|
||||||
|
|
||||||
cpu_fprintf(f, "SLB\tESID\t\t\tVSID\n");
|
qemu_printf("SLB\tESID\t\t\tVSID\n");
|
||||||
for (i = 0; i < cpu->hash64_opts->slb_size; i++) {
|
for (i = 0; i < cpu->hash64_opts->slb_size; i++) {
|
||||||
slbe = env->slb[i].esid;
|
slbe = env->slb[i].esid;
|
||||||
slbv = env->slb[i].vsid;
|
slbv = env->slb[i].vsid;
|
||||||
if (slbe == 0 && slbv == 0) {
|
if (slbe == 0 && slbv == 0) {
|
||||||
continue;
|
continue;
|
||||||
}
|
}
|
||||||
cpu_fprintf(f, "%d\t0x%016" PRIx64 "\t0x%016" PRIx64 "\n",
|
qemu_printf("%d\t0x%016" PRIx64 "\t0x%016" PRIx64 "\n",
|
||||||
i, slbe, slbv);
|
i, slbe, slbv);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -4,7 +4,7 @@
|
|||||||
#ifndef CONFIG_USER_ONLY
|
#ifndef CONFIG_USER_ONLY
|
||||||
|
|
||||||
#ifdef TARGET_PPC64
|
#ifdef TARGET_PPC64
|
||||||
void dump_slb(FILE *f, fprintf_function cpu_fprintf, PowerPCCPU *cpu);
|
void dump_slb(PowerPCCPU *cpu);
|
||||||
int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,
|
int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,
|
||||||
target_ulong esid, target_ulong vsid);
|
target_ulong esid, target_ulong vsid);
|
||||||
hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr);
|
hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr);
|
||||||
|
@ -29,6 +29,7 @@
|
|||||||
#include "exec/log.h"
|
#include "exec/log.h"
|
||||||
#include "helper_regs.h"
|
#include "helper_regs.h"
|
||||||
#include "qemu/error-report.h"
|
#include "qemu/error-report.h"
|
||||||
|
#include "qemu/qemu-print.h"
|
||||||
#include "mmu-book3s-v3.h"
|
#include "mmu-book3s-v3.h"
|
||||||
#include "mmu-radix64.h"
|
#include "mmu-radix64.h"
|
||||||
|
|
||||||
@ -1116,19 +1117,18 @@ static const char *book3e_tsize_to_str[32] = {
|
|||||||
"1T", "2T"
|
"1T", "2T"
|
||||||
};
|
};
|
||||||
|
|
||||||
static void mmubooke_dump_mmu(FILE *f, fprintf_function cpu_fprintf,
|
static void mmubooke_dump_mmu(CPUPPCState *env)
|
||||||
CPUPPCState *env)
|
|
||||||
{
|
{
|
||||||
ppcemb_tlb_t *entry;
|
ppcemb_tlb_t *entry;
|
||||||
int i;
|
int i;
|
||||||
|
|
||||||
if (kvm_enabled() && !env->kvm_sw_tlb) {
|
if (kvm_enabled() && !env->kvm_sw_tlb) {
|
||||||
cpu_fprintf(f, "Cannot access KVM TLB\n");
|
qemu_printf("Cannot access KVM TLB\n");
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
cpu_fprintf(f, "\nTLB:\n");
|
qemu_printf("\nTLB:\n");
|
||||||
cpu_fprintf(f, "Effective Physical Size PID Prot "
|
qemu_printf("Effective Physical Size PID Prot "
|
||||||
"Attr\n");
|
"Attr\n");
|
||||||
|
|
||||||
entry = &env->tlb.tlbe[0];
|
entry = &env->tlb.tlbe[0];
|
||||||
@ -1153,22 +1153,21 @@ static void mmubooke_dump_mmu(FILE *f, fprintf_function cpu_fprintf,
|
|||||||
} else {
|
} else {
|
||||||
snprintf(size_buf, sizeof(size_buf), "%3" PRId64 "k", size / KiB);
|
snprintf(size_buf, sizeof(size_buf), "%3" PRId64 "k", size / KiB);
|
||||||
}
|
}
|
||||||
cpu_fprintf(f, "0x%016" PRIx64 " 0x%016" PRIx64 " %s %-5u %08x %08x\n",
|
qemu_printf("0x%016" PRIx64 " 0x%016" PRIx64 " %s %-5u %08x %08x\n",
|
||||||
(uint64_t)ea, (uint64_t)pa, size_buf, (uint32_t)entry->PID,
|
(uint64_t)ea, (uint64_t)pa, size_buf, (uint32_t)entry->PID,
|
||||||
entry->prot, entry->attr);
|
entry->prot, entry->attr);
|
||||||
}
|
}
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static void mmubooke206_dump_one_tlb(FILE *f, fprintf_function cpu_fprintf,
|
static void mmubooke206_dump_one_tlb(CPUPPCState *env, int tlbn, int offset,
|
||||||
CPUPPCState *env, int tlbn, int offset,
|
|
||||||
int tlbsize)
|
int tlbsize)
|
||||||
{
|
{
|
||||||
ppcmas_tlb_t *entry;
|
ppcmas_tlb_t *entry;
|
||||||
int i;
|
int i;
|
||||||
|
|
||||||
cpu_fprintf(f, "\nTLB%d:\n", tlbn);
|
qemu_printf("\nTLB%d:\n", tlbn);
|
||||||
cpu_fprintf(f, "Effective Physical Size TID TS SRWX"
|
qemu_printf("Effective Physical Size TID TS SRWX"
|
||||||
" URWX WIMGE U0123\n");
|
" URWX WIMGE U0123\n");
|
||||||
|
|
||||||
entry = &env->tlb.tlbm[offset];
|
entry = &env->tlb.tlbm[offset];
|
||||||
@ -1185,7 +1184,7 @@ static void mmubooke206_dump_one_tlb(FILE *f, fprintf_function cpu_fprintf,
|
|||||||
ea = entry->mas2 & ~(size - 1);
|
ea = entry->mas2 & ~(size - 1);
|
||||||
pa = entry->mas7_3 & ~(size - 1);
|
pa = entry->mas7_3 & ~(size - 1);
|
||||||
|
|
||||||
cpu_fprintf(f, "0x%016" PRIx64 " 0x%016" PRIx64 " %4s %-5u %1u S%c%c%c"
|
qemu_printf("0x%016" PRIx64 " 0x%016" PRIx64 " %4s %-5u %1u S%c%c%c"
|
||||||
"U%c%c%c %c%c%c%c%c U%c%c%c%c\n",
|
"U%c%c%c %c%c%c%c%c U%c%c%c%c\n",
|
||||||
(uint64_t)ea, (uint64_t)pa,
|
(uint64_t)ea, (uint64_t)pa,
|
||||||
book3e_tsize_to_str[tsize],
|
book3e_tsize_to_str[tsize],
|
||||||
@ -1209,14 +1208,13 @@ static void mmubooke206_dump_one_tlb(FILE *f, fprintf_function cpu_fprintf,
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static void mmubooke206_dump_mmu(FILE *f, fprintf_function cpu_fprintf,
|
static void mmubooke206_dump_mmu(CPUPPCState *env)
|
||||||
CPUPPCState *env)
|
|
||||||
{
|
{
|
||||||
int offset = 0;
|
int offset = 0;
|
||||||
int i;
|
int i;
|
||||||
|
|
||||||
if (kvm_enabled() && !env->kvm_sw_tlb) {
|
if (kvm_enabled() && !env->kvm_sw_tlb) {
|
||||||
cpu_fprintf(f, "Cannot access KVM TLB\n");
|
qemu_printf("Cannot access KVM TLB\n");
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -1227,13 +1225,12 @@ static void mmubooke206_dump_mmu(FILE *f, fprintf_function cpu_fprintf,
|
|||||||
continue;
|
continue;
|
||||||
}
|
}
|
||||||
|
|
||||||
mmubooke206_dump_one_tlb(f, cpu_fprintf, env, i, offset, size);
|
mmubooke206_dump_one_tlb(env, i, offset, size);
|
||||||
offset += size;
|
offset += size;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static void mmu6xx_dump_BATs(FILE *f, fprintf_function cpu_fprintf,
|
static void mmu6xx_dump_BATs(CPUPPCState *env, int type)
|
||||||
CPUPPCState *env, int type)
|
|
||||||
{
|
{
|
||||||
target_ulong *BATlt, *BATut, *BATu, *BATl;
|
target_ulong *BATlt, *BATut, *BATu, *BATl;
|
||||||
target_ulong BEPIl, BEPIu, bl;
|
target_ulong BEPIl, BEPIu, bl;
|
||||||
@ -1256,7 +1253,7 @@ static void mmu6xx_dump_BATs(FILE *f, fprintf_function cpu_fprintf,
|
|||||||
BEPIu = *BATu & 0xF0000000;
|
BEPIu = *BATu & 0xF0000000;
|
||||||
BEPIl = *BATu & 0x0FFE0000;
|
BEPIl = *BATu & 0x0FFE0000;
|
||||||
bl = (*BATu & 0x00001FFC) << 15;
|
bl = (*BATu & 0x00001FFC) << 15;
|
||||||
cpu_fprintf(f, "%s BAT%d BATu " TARGET_FMT_lx
|
qemu_printf("%s BAT%d BATu " TARGET_FMT_lx
|
||||||
" BATl " TARGET_FMT_lx "\n\t" TARGET_FMT_lx " "
|
" BATl " TARGET_FMT_lx "\n\t" TARGET_FMT_lx " "
|
||||||
TARGET_FMT_lx " " TARGET_FMT_lx "\n",
|
TARGET_FMT_lx " " TARGET_FMT_lx "\n",
|
||||||
type == ACCESS_CODE ? "code" : "data", i,
|
type == ACCESS_CODE ? "code" : "data", i,
|
||||||
@ -1264,44 +1261,43 @@ static void mmu6xx_dump_BATs(FILE *f, fprintf_function cpu_fprintf,
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static void mmu6xx_dump_mmu(FILE *f, fprintf_function cpu_fprintf,
|
static void mmu6xx_dump_mmu(CPUPPCState *env)
|
||||||
CPUPPCState *env)
|
|
||||||
{
|
{
|
||||||
PowerPCCPU *cpu = ppc_env_get_cpu(env);
|
PowerPCCPU *cpu = ppc_env_get_cpu(env);
|
||||||
ppc6xx_tlb_t *tlb;
|
ppc6xx_tlb_t *tlb;
|
||||||
target_ulong sr;
|
target_ulong sr;
|
||||||
int type, way, entry, i;
|
int type, way, entry, i;
|
||||||
|
|
||||||
cpu_fprintf(f, "HTAB base = 0x%"HWADDR_PRIx"\n", ppc_hash32_hpt_base(cpu));
|
qemu_printf("HTAB base = 0x%"HWADDR_PRIx"\n", ppc_hash32_hpt_base(cpu));
|
||||||
cpu_fprintf(f, "HTAB mask = 0x%"HWADDR_PRIx"\n", ppc_hash32_hpt_mask(cpu));
|
qemu_printf("HTAB mask = 0x%"HWADDR_PRIx"\n", ppc_hash32_hpt_mask(cpu));
|
||||||
|
|
||||||
cpu_fprintf(f, "\nSegment registers:\n");
|
qemu_printf("\nSegment registers:\n");
|
||||||
for (i = 0; i < 32; i++) {
|
for (i = 0; i < 32; i++) {
|
||||||
sr = env->sr[i];
|
sr = env->sr[i];
|
||||||
if (sr & 0x80000000) {
|
if (sr & 0x80000000) {
|
||||||
cpu_fprintf(f, "%02d T=%d Ks=%d Kp=%d BUID=0x%03x "
|
qemu_printf("%02d T=%d Ks=%d Kp=%d BUID=0x%03x "
|
||||||
"CNTLR_SPEC=0x%05x\n", i,
|
"CNTLR_SPEC=0x%05x\n", i,
|
||||||
sr & 0x80000000 ? 1 : 0, sr & 0x40000000 ? 1 : 0,
|
sr & 0x80000000 ? 1 : 0, sr & 0x40000000 ? 1 : 0,
|
||||||
sr & 0x20000000 ? 1 : 0, (uint32_t)((sr >> 20) & 0x1FF),
|
sr & 0x20000000 ? 1 : 0, (uint32_t)((sr >> 20) & 0x1FF),
|
||||||
(uint32_t)(sr & 0xFFFFF));
|
(uint32_t)(sr & 0xFFFFF));
|
||||||
} else {
|
} else {
|
||||||
cpu_fprintf(f, "%02d T=%d Ks=%d Kp=%d N=%d VSID=0x%06x\n", i,
|
qemu_printf("%02d T=%d Ks=%d Kp=%d N=%d VSID=0x%06x\n", i,
|
||||||
sr & 0x80000000 ? 1 : 0, sr & 0x40000000 ? 1 : 0,
|
sr & 0x80000000 ? 1 : 0, sr & 0x40000000 ? 1 : 0,
|
||||||
sr & 0x20000000 ? 1 : 0, sr & 0x10000000 ? 1 : 0,
|
sr & 0x20000000 ? 1 : 0, sr & 0x10000000 ? 1 : 0,
|
||||||
(uint32_t)(sr & 0x00FFFFFF));
|
(uint32_t)(sr & 0x00FFFFFF));
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
cpu_fprintf(f, "\nBATs:\n");
|
qemu_printf("\nBATs:\n");
|
||||||
mmu6xx_dump_BATs(f, cpu_fprintf, env, ACCESS_INT);
|
mmu6xx_dump_BATs(env, ACCESS_INT);
|
||||||
mmu6xx_dump_BATs(f, cpu_fprintf, env, ACCESS_CODE);
|
mmu6xx_dump_BATs(env, ACCESS_CODE);
|
||||||
|
|
||||||
if (env->id_tlbs != 1) {
|
if (env->id_tlbs != 1) {
|
||||||
cpu_fprintf(f, "ERROR: 6xx MMU should have separated TLB"
|
qemu_printf("ERROR: 6xx MMU should have separated TLB"
|
||||||
" for code and data\n");
|
" for code and data\n");
|
||||||
}
|
}
|
||||||
|
|
||||||
cpu_fprintf(f, "\nTLBs [EPN EPN + SIZE]\n");
|
qemu_printf("\nTLBs [EPN EPN + SIZE]\n");
|
||||||
|
|
||||||
for (type = 0; type < 2; type++) {
|
for (type = 0; type < 2; type++) {
|
||||||
for (way = 0; way < env->nb_ways; way++) {
|
for (way = 0; way < env->nb_ways; way++) {
|
||||||
@ -1310,7 +1306,7 @@ static void mmu6xx_dump_mmu(FILE *f, fprintf_function cpu_fprintf,
|
|||||||
entry++) {
|
entry++) {
|
||||||
|
|
||||||
tlb = &env->tlb.tlb6[entry];
|
tlb = &env->tlb.tlb6[entry];
|
||||||
cpu_fprintf(f, "%s TLB %02d/%02d way:%d %s ["
|
qemu_printf("%s TLB %02d/%02d way:%d %s ["
|
||||||
TARGET_FMT_lx " " TARGET_FMT_lx "]\n",
|
TARGET_FMT_lx " " TARGET_FMT_lx "]\n",
|
||||||
type ? "code" : "data", entry % env->nb_tlb,
|
type ? "code" : "data", entry % env->nb_tlb,
|
||||||
env->nb_tlb, way,
|
env->nb_tlb, way,
|
||||||
@ -1321,31 +1317,31 @@ static void mmu6xx_dump_mmu(FILE *f, fprintf_function cpu_fprintf,
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env)
|
void dump_mmu(CPUPPCState *env)
|
||||||
{
|
{
|
||||||
switch (env->mmu_model) {
|
switch (env->mmu_model) {
|
||||||
case POWERPC_MMU_BOOKE:
|
case POWERPC_MMU_BOOKE:
|
||||||
mmubooke_dump_mmu(f, cpu_fprintf, env);
|
mmubooke_dump_mmu(env);
|
||||||
break;
|
break;
|
||||||
case POWERPC_MMU_BOOKE206:
|
case POWERPC_MMU_BOOKE206:
|
||||||
mmubooke206_dump_mmu(f, cpu_fprintf, env);
|
mmubooke206_dump_mmu(env);
|
||||||
break;
|
break;
|
||||||
case POWERPC_MMU_SOFT_6xx:
|
case POWERPC_MMU_SOFT_6xx:
|
||||||
case POWERPC_MMU_SOFT_74xx:
|
case POWERPC_MMU_SOFT_74xx:
|
||||||
mmu6xx_dump_mmu(f, cpu_fprintf, env);
|
mmu6xx_dump_mmu(env);
|
||||||
break;
|
break;
|
||||||
#if defined(TARGET_PPC64)
|
#if defined(TARGET_PPC64)
|
||||||
case POWERPC_MMU_64B:
|
case POWERPC_MMU_64B:
|
||||||
case POWERPC_MMU_2_03:
|
case POWERPC_MMU_2_03:
|
||||||
case POWERPC_MMU_2_06:
|
case POWERPC_MMU_2_06:
|
||||||
case POWERPC_MMU_2_07:
|
case POWERPC_MMU_2_07:
|
||||||
dump_slb(f, cpu_fprintf, ppc_env_get_cpu(env));
|
dump_slb(ppc_env_get_cpu(env));
|
||||||
break;
|
break;
|
||||||
case POWERPC_MMU_3_00:
|
case POWERPC_MMU_3_00:
|
||||||
if (ppc64_v3_radix(ppc_env_get_cpu(env))) {
|
if (ppc64_v3_radix(ppc_env_get_cpu(env))) {
|
||||||
/* TODO - Unsupported */
|
/* TODO - Unsupported */
|
||||||
} else {
|
} else {
|
||||||
dump_slb(f, cpu_fprintf, ppc_env_get_cpu(env));
|
dump_slb(ppc_env_get_cpu(env));
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
@ -66,7 +66,7 @@ void hmp_info_tlb(Monitor *mon, const QDict *qdict)
|
|||||||
monitor_printf(mon, "No CPU available\n");
|
monitor_printf(mon, "No CPU available\n");
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
dump_mmu((FILE*)mon, (fprintf_function)monitor_printf, env1);
|
dump_mmu(env1);
|
||||||
}
|
}
|
||||||
|
|
||||||
const MonitorDef monitor_defs[] = {
|
const MonitorDef monitor_defs[] = {
|
||||||
|
@ -583,7 +583,7 @@ void sparc_cpu_list(void);
|
|||||||
int sparc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw,
|
int sparc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw,
|
||||||
int mmu_idx);
|
int mmu_idx);
|
||||||
target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev);
|
target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev);
|
||||||
void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env);
|
void dump_mmu(CPUSPARCState *env);
|
||||||
|
|
||||||
#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
|
#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
|
||||||
int sparc_cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
|
int sparc_cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
|
||||||
|
@ -198,7 +198,7 @@ static void demap_tlb(SparcTLBEntry *tlb, target_ulong demap_addr,
|
|||||||
replace_tlb_entry(&tlb[i], 0, 0, env1);
|
replace_tlb_entry(&tlb[i], 0, 0, env1);
|
||||||
#ifdef DEBUG_MMU
|
#ifdef DEBUG_MMU
|
||||||
DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu, i);
|
DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu, i);
|
||||||
dump_mmu(stdout, fprintf, env1);
|
dump_mmu(env1);
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -260,7 +260,7 @@ static void replace_tlb_1bit_lru(SparcTLBEntry *tlb,
|
|||||||
replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
|
replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
|
||||||
#ifdef DEBUG_MMU
|
#ifdef DEBUG_MMU
|
||||||
DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu, i);
|
DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu, i);
|
||||||
dump_mmu(stdout, fprintf, env1);
|
dump_mmu(env1);
|
||||||
#endif
|
#endif
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
@ -279,7 +279,7 @@ static void replace_tlb_1bit_lru(SparcTLBEntry *tlb,
|
|||||||
#ifdef DEBUG_MMU
|
#ifdef DEBUG_MMU
|
||||||
DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",
|
DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",
|
||||||
strmmu, (replace_used ? "used" : "unused"), i);
|
strmmu, (replace_used ? "used" : "unused"), i);
|
||||||
dump_mmu(stdout, fprintf, env1);
|
dump_mmu(env1);
|
||||||
#endif
|
#endif
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
@ -886,7 +886,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val,
|
|||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
#ifdef DEBUG_MMU
|
#ifdef DEBUG_MMU
|
||||||
dump_mmu(stdout, fprintf, env);
|
dump_mmu(env);
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
@ -941,7 +941,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val,
|
|||||||
reg, oldreg, env->mmuregs[reg]);
|
reg, oldreg, env->mmuregs[reg]);
|
||||||
}
|
}
|
||||||
#ifdef DEBUG_MMU
|
#ifdef DEBUG_MMU
|
||||||
dump_mmu(stdout, fprintf, env);
|
dump_mmu(env);
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
@ -1634,7 +1634,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
|
|||||||
PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
|
PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
|
||||||
}
|
}
|
||||||
#ifdef DEBUG_MMU
|
#ifdef DEBUG_MMU
|
||||||
dump_mmu(stdout, fprintf, env);
|
dump_mmu(env);
|
||||||
#endif
|
#endif
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
@ -1658,7 +1658,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
|
|||||||
}
|
}
|
||||||
#ifdef DEBUG_MMU
|
#ifdef DEBUG_MMU
|
||||||
DPRINTF_MMU("immu data access replaced entry [%i]\n", i);
|
DPRINTF_MMU("immu data access replaced entry [%i]\n", i);
|
||||||
dump_mmu(stdout, fprintf, env);
|
dump_mmu(env);
|
||||||
#endif
|
#endif
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
@ -1718,7 +1718,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
|
|||||||
PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
|
PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
|
||||||
}
|
}
|
||||||
#ifdef DEBUG_MMU
|
#ifdef DEBUG_MMU
|
||||||
dump_mmu(stdout, fprintf, env);
|
dump_mmu(env);
|
||||||
#endif
|
#endif
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
@ -1740,7 +1740,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
|
|||||||
}
|
}
|
||||||
#ifdef DEBUG_MMU
|
#ifdef DEBUG_MMU
|
||||||
DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i);
|
DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i);
|
||||||
dump_mmu(stdout, fprintf, env);
|
dump_mmu(env);
|
||||||
#endif
|
#endif
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
@ -20,6 +20,7 @@
|
|||||||
#include "qemu/osdep.h"
|
#include "qemu/osdep.h"
|
||||||
#include "cpu.h"
|
#include "cpu.h"
|
||||||
#include "exec/exec-all.h"
|
#include "exec/exec-all.h"
|
||||||
|
#include "qemu/qemu-print.h"
|
||||||
#include "trace.h"
|
#include "trace.h"
|
||||||
|
|
||||||
/* Sparc MMU emulation */
|
/* Sparc MMU emulation */
|
||||||
@ -320,7 +321,7 @@ target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev)
|
|||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env)
|
void dump_mmu(CPUSPARCState *env)
|
||||||
{
|
{
|
||||||
CPUState *cs = CPU(sparc_env_get_cpu(env));
|
CPUState *cs = CPU(sparc_env_get_cpu(env));
|
||||||
target_ulong va, va1, va2;
|
target_ulong va, va1, va2;
|
||||||
@ -330,26 +331,26 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env)
|
|||||||
|
|
||||||
pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
|
pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
|
||||||
pde = ldl_phys(cs->as, pde_ptr);
|
pde = ldl_phys(cs->as, pde_ptr);
|
||||||
(*cpu_fprintf)(f, "Root ptr: " TARGET_FMT_plx ", ctx: %d\n",
|
qemu_printf("Root ptr: " TARGET_FMT_plx ", ctx: %d\n",
|
||||||
(hwaddr)env->mmuregs[1] << 4, env->mmuregs[2]);
|
(hwaddr)env->mmuregs[1] << 4, env->mmuregs[2]);
|
||||||
for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
|
for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
|
||||||
pde = mmu_probe(env, va, 2);
|
pde = mmu_probe(env, va, 2);
|
||||||
if (pde) {
|
if (pde) {
|
||||||
pa = cpu_get_phys_page_debug(cs, va);
|
pa = cpu_get_phys_page_debug(cs, va);
|
||||||
(*cpu_fprintf)(f, "VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
|
qemu_printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
|
||||||
" PDE: " TARGET_FMT_lx "\n", va, pa, pde);
|
" PDE: " TARGET_FMT_lx "\n", va, pa, pde);
|
||||||
for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
|
for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
|
||||||
pde = mmu_probe(env, va1, 1);
|
pde = mmu_probe(env, va1, 1);
|
||||||
if (pde) {
|
if (pde) {
|
||||||
pa = cpu_get_phys_page_debug(cs, va1);
|
pa = cpu_get_phys_page_debug(cs, va1);
|
||||||
(*cpu_fprintf)(f, " VA: " TARGET_FMT_lx ", PA: "
|
qemu_printf(" VA: " TARGET_FMT_lx ", PA: "
|
||||||
TARGET_FMT_plx " PDE: " TARGET_FMT_lx "\n",
|
TARGET_FMT_plx " PDE: " TARGET_FMT_lx "\n",
|
||||||
va1, pa, pde);
|
va1, pa, pde);
|
||||||
for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
|
for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
|
||||||
pde = mmu_probe(env, va2, 0);
|
pde = mmu_probe(env, va2, 0);
|
||||||
if (pde) {
|
if (pde) {
|
||||||
pa = cpu_get_phys_page_debug(cs, va2);
|
pa = cpu_get_phys_page_debug(cs, va2);
|
||||||
(*cpu_fprintf)(f, " VA: " TARGET_FMT_lx ", PA: "
|
qemu_printf(" VA: " TARGET_FMT_lx ", PA: "
|
||||||
TARGET_FMT_plx " PTE: "
|
TARGET_FMT_plx " PTE: "
|
||||||
TARGET_FMT_lx "\n",
|
TARGET_FMT_lx "\n",
|
||||||
va2, pa, pde);
|
va2, pa, pde);
|
||||||
@ -739,21 +740,21 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
|
|||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
|
||||||
void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env)
|
void dump_mmu(CPUSPARCState *env)
|
||||||
{
|
{
|
||||||
unsigned int i;
|
unsigned int i;
|
||||||
const char *mask;
|
const char *mask;
|
||||||
|
|
||||||
(*cpu_fprintf)(f, "MMU contexts: Primary: %" PRId64 ", Secondary: %"
|
qemu_printf("MMU contexts: Primary: %" PRId64 ", Secondary: %"
|
||||||
PRId64 "\n",
|
PRId64 "\n",
|
||||||
env->dmmu.mmu_primary_context,
|
env->dmmu.mmu_primary_context,
|
||||||
env->dmmu.mmu_secondary_context);
|
env->dmmu.mmu_secondary_context);
|
||||||
(*cpu_fprintf)(f, "DMMU Tag Access: %" PRIx64 ", TSB Tag Target: %" PRIx64
|
qemu_printf("DMMU Tag Access: %" PRIx64 ", TSB Tag Target: %" PRIx64
|
||||||
"\n", env->dmmu.tag_access, env->dmmu.tsb_tag_target);
|
"\n", env->dmmu.tag_access, env->dmmu.tsb_tag_target);
|
||||||
if ((env->lsu & DMMU_E) == 0) {
|
if ((env->lsu & DMMU_E) == 0) {
|
||||||
(*cpu_fprintf)(f, "DMMU disabled\n");
|
qemu_printf("DMMU disabled\n");
|
||||||
} else {
|
} else {
|
||||||
(*cpu_fprintf)(f, "DMMU dump\n");
|
qemu_printf("DMMU dump\n");
|
||||||
for (i = 0; i < 64; i++) {
|
for (i = 0; i < 64; i++) {
|
||||||
switch (TTE_PGSIZE(env->dtlb[i].tte)) {
|
switch (TTE_PGSIZE(env->dtlb[i].tte)) {
|
||||||
default:
|
default:
|
||||||
@ -771,7 +772,7 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env)
|
|||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
if (TTE_IS_VALID(env->dtlb[i].tte)) {
|
if (TTE_IS_VALID(env->dtlb[i].tte)) {
|
||||||
(*cpu_fprintf)(f, "[%02u] VA: %" PRIx64 ", PA: %llx"
|
qemu_printf("[%02u] VA: %" PRIx64 ", PA: %llx"
|
||||||
", %s, %s, %s, %s, ctx %" PRId64 " %s\n",
|
", %s, %s, %s, %s, ctx %" PRId64 " %s\n",
|
||||||
i,
|
i,
|
||||||
env->dtlb[i].tag & (uint64_t)~0x1fffULL,
|
env->dtlb[i].tag & (uint64_t)~0x1fffULL,
|
||||||
@ -788,9 +789,9 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env)
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
if ((env->lsu & IMMU_E) == 0) {
|
if ((env->lsu & IMMU_E) == 0) {
|
||||||
(*cpu_fprintf)(f, "IMMU disabled\n");
|
qemu_printf("IMMU disabled\n");
|
||||||
} else {
|
} else {
|
||||||
(*cpu_fprintf)(f, "IMMU dump\n");
|
qemu_printf("IMMU dump\n");
|
||||||
for (i = 0; i < 64; i++) {
|
for (i = 0; i < 64; i++) {
|
||||||
switch (TTE_PGSIZE(env->itlb[i].tte)) {
|
switch (TTE_PGSIZE(env->itlb[i].tte)) {
|
||||||
default:
|
default:
|
||||||
@ -808,7 +809,7 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env)
|
|||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
if (TTE_IS_VALID(env->itlb[i].tte)) {
|
if (TTE_IS_VALID(env->itlb[i].tte)) {
|
||||||
(*cpu_fprintf)(f, "[%02u] VA: %" PRIx64 ", PA: %llx"
|
qemu_printf("[%02u] VA: %" PRIx64 ", PA: %llx"
|
||||||
", %s, %s, %s, ctx %" PRId64 " %s\n",
|
", %s, %s, %s, ctx %" PRId64 " %s\n",
|
||||||
i,
|
i,
|
||||||
env->itlb[i].tag & (uint64_t)~0x1fffULL,
|
env->itlb[i].tag & (uint64_t)~0x1fffULL,
|
||||||
|
@ -36,7 +36,7 @@ void hmp_info_tlb(Monitor *mon, const QDict *qdict)
|
|||||||
monitor_printf(mon, "No CPU available\n");
|
monitor_printf(mon, "No CPU available\n");
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
dump_mmu((FILE*)mon, (fprintf_function)monitor_printf, env1);
|
dump_mmu(env1);
|
||||||
}
|
}
|
||||||
|
|
||||||
#ifndef TARGET_SPARC64
|
#ifndef TARGET_SPARC64
|
||||||
|
@ -673,7 +673,7 @@ int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
|
|||||||
uint32_t vaddr, int is_write, int mmu_idx,
|
uint32_t vaddr, int is_write, int mmu_idx,
|
||||||
uint32_t *paddr, uint32_t *page_size, unsigned *access);
|
uint32_t *paddr, uint32_t *page_size, unsigned *access);
|
||||||
void reset_mmu(CPUXtensaState *env);
|
void reset_mmu(CPUXtensaState *env);
|
||||||
void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env);
|
void dump_mmu(CPUXtensaState *env);
|
||||||
|
|
||||||
static inline MemoryRegion *xtensa_get_er_region(CPUXtensaState *env)
|
static inline MemoryRegion *xtensa_get_er_region(CPUXtensaState *env)
|
||||||
{
|
{
|
||||||
|
@ -27,6 +27,7 @@
|
|||||||
|
|
||||||
#include "qemu/osdep.h"
|
#include "qemu/osdep.h"
|
||||||
#include "qemu/main-loop.h"
|
#include "qemu/main-loop.h"
|
||||||
|
#include "qemu/qemu-print.h"
|
||||||
#include "qemu/units.h"
|
#include "qemu/units.h"
|
||||||
#include "cpu.h"
|
#include "cpu.h"
|
||||||
#include "exec/helper-proto.h"
|
#include "exec/helper-proto.h"
|
||||||
@ -740,8 +741,7 @@ int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static void dump_tlb(FILE *f, fprintf_function cpu_fprintf,
|
static void dump_tlb(CPUXtensaState *env, bool dtlb)
|
||||||
CPUXtensaState *env, bool dtlb)
|
|
||||||
{
|
{
|
||||||
unsigned wi, ei;
|
unsigned wi, ei;
|
||||||
const xtensa_tlb *conf =
|
const xtensa_tlb *conf =
|
||||||
@ -780,13 +780,11 @@ static void dump_tlb(FILE *f, fprintf_function cpu_fprintf,
|
|||||||
|
|
||||||
if (print_header) {
|
if (print_header) {
|
||||||
print_header = false;
|
print_header = false;
|
||||||
cpu_fprintf(f, "Way %u (%d %s)\n", wi, sz, sz_text);
|
qemu_printf("Way %u (%d %s)\n", wi, sz, sz_text);
|
||||||
cpu_fprintf(f,
|
qemu_printf("\tVaddr Paddr ASID Attr RWX Cache\n"
|
||||||
"\tVaddr Paddr ASID Attr RWX Cache\n"
|
|
||||||
"\t---------- ---------- ---- ---- --- -------\n");
|
"\t---------- ---------- ---- ---- --- -------\n");
|
||||||
}
|
}
|
||||||
cpu_fprintf(f,
|
qemu_printf("\t0x%08x 0x%08x 0x%02x 0x%02x %c%c%c %-7s\n",
|
||||||
"\t0x%08x 0x%08x 0x%02x 0x%02x %c%c%c %-7s\n",
|
|
||||||
entry->vaddr,
|
entry->vaddr,
|
||||||
entry->paddr,
|
entry->paddr,
|
||||||
entry->asid,
|
entry->asid,
|
||||||
@ -801,18 +799,18 @@ static void dump_tlb(FILE *f, fprintf_function cpu_fprintf,
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env)
|
void dump_mmu(CPUXtensaState *env)
|
||||||
{
|
{
|
||||||
if (xtensa_option_bits_enabled(env->config,
|
if (xtensa_option_bits_enabled(env->config,
|
||||||
XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
|
XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
|
||||||
XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION) |
|
XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION) |
|
||||||
XTENSA_OPTION_BIT(XTENSA_OPTION_MMU))) {
|
XTENSA_OPTION_BIT(XTENSA_OPTION_MMU))) {
|
||||||
|
|
||||||
cpu_fprintf(f, "ITLB:\n");
|
qemu_printf("ITLB:\n");
|
||||||
dump_tlb(f, cpu_fprintf, env, false);
|
dump_tlb(env, false);
|
||||||
cpu_fprintf(f, "\nDTLB:\n");
|
qemu_printf("\nDTLB:\n");
|
||||||
dump_tlb(f, cpu_fprintf, env, true);
|
dump_tlb(env, true);
|
||||||
} else {
|
} else {
|
||||||
cpu_fprintf(f, "No TLB for this CPU core\n");
|
qemu_printf("No TLB for this CPU core\n");
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -35,5 +35,5 @@ void hmp_info_tlb(Monitor *mon, const QDict *qdict)
|
|||||||
monitor_printf(mon, "No CPU available\n");
|
monitor_printf(mon, "No CPU available\n");
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
dump_mmu((FILE*)mon, (fprintf_function)monitor_printf, env1);
|
dump_mmu(env1);
|
||||||
}
|
}
|
||||||
|
Loading…
Reference in New Issue
Block a user