mirror of https://gitlab.com/qemu-project/qemu
target-s390: Convert AND, OR, XOR, INSERT IMMEDIATE
Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson
parent
b9bca3e57a
commit
facfc86487
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@ -49,6 +49,13 @@
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C(0xb980, NGR, RRE, Z, r1, r2, r1, 0, and, nz64)
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C(0xb9e4, NGRK, RRF_a, DO, r2, r3, r1, 0, and, nz64)
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C(0xe380, NG, RXY_a, Z, r1, m2_64, r1, 0, and, nz64)
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/* AND IMMEDIATE */
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D(0xc00a, NIHF, RIL_a, EI, r1_o, i2_32u, r1, 0, andi, 0, 0x2020)
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D(0xc00b, NILF, RIL_a, EI, r1_o, i2_32u, r1, 0, andi, 0, 0x2000)
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D(0xa504, NIHH, RI_a, Z, r1_o, i2_16u, r1, 0, andi, 0, 0x1030)
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D(0xa505, NIHL, RI_a, Z, r1_o, i2_16u, r1, 0, andi, 0, 0x1020)
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D(0xa506, NILH, RI_a, Z, r1_o, i2_16u, r1, 0, andi, 0, 0x1010)
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D(0xa507, NILL, RI_a, Z, r1_o, i2_16u, r1, 0, andi, 0, 0x1000)
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/* COMPARE */
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C(0x1900, CR, RR_a, Z, r1_o, r2_o, 0, 0, 0, cmps32)
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@ -106,6 +113,17 @@
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C(0xb982, XGR, RRE, Z, r1, r2, r1, 0, xor, nz64)
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C(0xb9e7, XGRK, RRF_a, DO, r2, r3, r1, 0, xor, nz64)
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C(0xe382, XG, RXY_a, Z, r1, m2_64, r1, 0, xor, nz64)
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/* EXCLUSIVE OR IMMEDIATE */
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D(0xc006, XIHF, RIL_a, EI, r1_o, i2_32u, r1, 0, xori, 0, 0x2020)
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D(0xc007, XILF, RIL_a, EI, r1_o, i2_32u, r1, 0, xori, 0, 0x2000)
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/* INSERT IMMEDIATE */
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D(0xc008, IIHF, RIL_a, EI, r1_o, i2_32u, r1, 0, insi, 0, 0x2020)
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D(0xc009, IILF, RIL_a, EI, r1_o, i2_32u, r1, 0, insi, 0, 0x2000)
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D(0xa500, IIHH, RI_a, Z, r1_o, i2_16u, r1, 0, insi, 0, 0x1030)
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D(0xa501, IIHL, RI_a, Z, r1_o, i2_16u, r1, 0, insi, 0, 0x1020)
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D(0xa502, IILH, RI_a, Z, r1_o, i2_16u, r1, 0, insi, 0, 0x1010)
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D(0xa503, IILL, RI_a, Z, r1_o, i2_16u, r1, 0, insi, 0, 0x1000)
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/* LOAD */
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C(0x1800, LR, RR_a, Z, 0, r2_o, 0, cond_r1r2_32, mov2, 0)
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@ -223,6 +241,13 @@
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C(0xb981, OGR, RRE, Z, r1, r2, r1, 0, or, nz64)
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C(0xb9e6, OGRK, RRF_a, DO, r2, r3, r1, 0, or, nz64)
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C(0xe381, OG, RXY_a, Z, r1, m2_64, r1, 0, or, nz64)
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/* OR IMMEDIATE */
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D(0xc00c, OIHF, RIL_a, EI, r1_o, i2_32u, r1, 0, ori, 0, 0x2020)
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D(0xc00d, OILF, RIL_a, EI, r1_o, i2_32u, r1, 0, ori, 0, 0x2000)
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D(0xa508, OIHH, RI_a, Z, r1_o, i2_16u, r1, 0, ori, 0, 0x1030)
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D(0xa509, OIHL, RI_a, Z, r1_o, i2_16u, r1, 0, ori, 0, 0x1020)
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D(0xa50a, OILH, RI_a, Z, r1_o, i2_16u, r1, 0, ori, 0, 0x1010)
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D(0xa50b, OILL, RI_a, Z, r1_o, i2_16u, r1, 0, ori, 0, 0x1000)
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/* SUBTRACT */
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C(0x1b00, SR, RR_a, Z, r1, r2, new, r1_32, sub, subs32)
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@ -1875,141 +1875,6 @@ static void disas_ed(CPUS390XState *env, DisasContext *s, int op, int r1,
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tcg_temp_free_i64(addr);
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}
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static void disas_a5(CPUS390XState *env, DisasContext *s, int op, int r1,
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int i2)
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{
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TCGv_i64 tmp, tmp2;
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TCGv_i32 tmp32;
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LOG_DISAS("disas_a5: op 0x%x r1 %d i2 0x%x\n", op, r1, i2);
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switch (op) {
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case 0x0: /* IIHH R1,I2 [RI] */
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tmp = tcg_const_i64(i2);
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tcg_gen_deposit_i64(regs[r1], regs[r1], tmp, 48, 16);
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tcg_temp_free_i64(tmp);
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break;
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case 0x1: /* IIHL R1,I2 [RI] */
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tmp = tcg_const_i64(i2);
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tcg_gen_deposit_i64(regs[r1], regs[r1], tmp, 32, 16);
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tcg_temp_free_i64(tmp);
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break;
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case 0x2: /* IILH R1,I2 [RI] */
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tmp = tcg_const_i64(i2);
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tcg_gen_deposit_i64(regs[r1], regs[r1], tmp, 16, 16);
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tcg_temp_free_i64(tmp);
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break;
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case 0x3: /* IILL R1,I2 [RI] */
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tmp = tcg_const_i64(i2);
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tcg_gen_deposit_i64(regs[r1], regs[r1], tmp, 0, 16);
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tcg_temp_free_i64(tmp);
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break;
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case 0x4: /* NIHH R1,I2 [RI] */
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case 0x8: /* OIHH R1,I2 [RI] */
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tmp = load_reg(r1);
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tmp32 = tcg_temp_new_i32();
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switch (op) {
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case 0x4:
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tmp2 = tcg_const_i64((((uint64_t)i2) << 48)
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| 0x0000ffffffffffffULL);
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tcg_gen_and_i64(tmp, tmp, tmp2);
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break;
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case 0x8:
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tmp2 = tcg_const_i64(((uint64_t)i2) << 48);
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tcg_gen_or_i64(tmp, tmp, tmp2);
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break;
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default:
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tcg_abort();
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}
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store_reg(r1, tmp);
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tcg_gen_shri_i64(tmp2, tmp, 48);
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tcg_gen_trunc_i64_i32(tmp32, tmp2);
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set_cc_nz_u32(s, tmp32);
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tcg_temp_free_i64(tmp2);
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tcg_temp_free_i32(tmp32);
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tcg_temp_free_i64(tmp);
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break;
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case 0x5: /* NIHL R1,I2 [RI] */
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case 0x9: /* OIHL R1,I2 [RI] */
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tmp = load_reg(r1);
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tmp32 = tcg_temp_new_i32();
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switch (op) {
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case 0x5:
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tmp2 = tcg_const_i64((((uint64_t)i2) << 32)
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| 0xffff0000ffffffffULL);
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tcg_gen_and_i64(tmp, tmp, tmp2);
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break;
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case 0x9:
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tmp2 = tcg_const_i64(((uint64_t)i2) << 32);
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tcg_gen_or_i64(tmp, tmp, tmp2);
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break;
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default:
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tcg_abort();
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}
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store_reg(r1, tmp);
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tcg_gen_shri_i64(tmp2, tmp, 32);
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tcg_gen_trunc_i64_i32(tmp32, tmp2);
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tcg_gen_andi_i32(tmp32, tmp32, 0xffff);
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set_cc_nz_u32(s, tmp32);
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tcg_temp_free_i64(tmp2);
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tcg_temp_free_i32(tmp32);
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tcg_temp_free_i64(tmp);
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break;
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case 0x6: /* NILH R1,I2 [RI] */
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case 0xa: /* OILH R1,I2 [RI] */
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tmp = load_reg(r1);
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tmp32 = tcg_temp_new_i32();
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switch (op) {
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case 0x6:
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tmp2 = tcg_const_i64((((uint64_t)i2) << 16)
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| 0xffffffff0000ffffULL);
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tcg_gen_and_i64(tmp, tmp, tmp2);
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break;
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case 0xa:
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tmp2 = tcg_const_i64(((uint64_t)i2) << 16);
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tcg_gen_or_i64(tmp, tmp, tmp2);
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break;
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default:
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tcg_abort();
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}
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store_reg(r1, tmp);
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tcg_gen_shri_i64(tmp, tmp, 16);
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tcg_gen_trunc_i64_i32(tmp32, tmp);
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tcg_gen_andi_i32(tmp32, tmp32, 0xffff);
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set_cc_nz_u32(s, tmp32);
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tcg_temp_free_i64(tmp2);
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tcg_temp_free_i32(tmp32);
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tcg_temp_free_i64(tmp);
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break;
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case 0x7: /* NILL R1,I2 [RI] */
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case 0xb: /* OILL R1,I2 [RI] */
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tmp = load_reg(r1);
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tmp32 = tcg_temp_new_i32();
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switch (op) {
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case 0x7:
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tmp2 = tcg_const_i64(i2 | 0xffffffffffff0000ULL);
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tcg_gen_and_i64(tmp, tmp, tmp2);
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break;
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case 0xb:
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tmp2 = tcg_const_i64(i2);
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tcg_gen_or_i64(tmp, tmp, tmp2);
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break;
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default:
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tcg_abort();
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}
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store_reg(r1, tmp);
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tcg_gen_trunc_i64_i32(tmp32, tmp);
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tcg_gen_andi_i32(tmp32, tmp32, 0xffff);
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set_cc_nz_u32(s, tmp32); /* signedness should not matter here */
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tcg_temp_free_i64(tmp2);
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tcg_temp_free_i32(tmp32);
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tcg_temp_free_i64(tmp);
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break;
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default:
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LOG_DISAS("illegal a5 operation 0x%x\n", op);
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gen_illegal_opcode(s);
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return;
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}
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}
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static void disas_a7(CPUS390XState *env, DisasContext *s, int op, int r1,
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int i2)
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{
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@ -2918,44 +2783,6 @@ static void disas_c0(CPUS390XState *env, DisasContext *s, int op, int r1, int i2
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gen_goto_tb(s, 0, target);
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s->is_jmp = DISAS_TB_JUMP;
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break;
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case 0x7: /* XILF R1,I2 [RIL] */
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case 0xb: /* NILF R1,I2 [RIL] */
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case 0xd: /* OILF R1,I2 [RIL] */
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tmp32_1 = load_reg32(r1);
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switch (op) {
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case 0x7:
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tcg_gen_xori_i32(tmp32_1, tmp32_1, (uint32_t)i2);
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break;
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case 0xb:
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tcg_gen_andi_i32(tmp32_1, tmp32_1, (uint32_t)i2);
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break;
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case 0xd:
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tcg_gen_ori_i32(tmp32_1, tmp32_1, (uint32_t)i2);
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break;
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default:
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tcg_abort();
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}
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store_reg32(r1, tmp32_1);
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set_cc_nz_u32(s, tmp32_1);
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tcg_temp_free_i32(tmp32_1);
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break;
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case 0x9: /* IILF R1,I2 [RIL] */
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tmp32_1 = tcg_const_i32((uint32_t)i2);
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store_reg32(r1, tmp32_1);
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tcg_temp_free_i32(tmp32_1);
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break;
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case 0xa: /* NIHF R1,I2 [RIL] */
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tmp = load_reg(r1);
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tmp32_1 = tcg_temp_new_i32();
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tcg_gen_andi_i64(tmp, tmp, (((uint64_t)((uint32_t)i2)) << 32)
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| 0xffffffffULL);
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store_reg(r1, tmp);
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tcg_gen_shri_i64(tmp, tmp, 32);
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tcg_gen_trunc_i64_i32(tmp32_1, tmp);
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set_cc_nz_u32(s, tmp32_1);
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tcg_temp_free_i64(tmp);
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tcg_temp_free_i32(tmp32_1);
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break;
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default:
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LOG_DISAS("illegal c0 operation 0x%x\n", op);
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gen_illegal_opcode(s);
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@ -3487,13 +3314,6 @@ static void disas_s390_insn(CPUS390XState *env, DisasContext *s)
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tcg_temp_free_i32(tmp32_1);
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tcg_temp_free_i32(tmp32_2);
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break;
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case 0xa5:
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insn = ld_code4(env, s->pc);
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r1 = (insn >> 20) & 0xf;
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op = (insn >> 16) & 0xf;
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i2 = insn & 0xffff;
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disas_a5(env, s, op, r1, i2);
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break;
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case 0xa7:
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insn = ld_code4(env, s->pc);
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r1 = (insn >> 20) & 0xf;
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@ -4112,6 +3932,31 @@ static ExitStatus op_and(DisasContext *s, DisasOps *o)
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return NO_EXIT;
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}
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static ExitStatus op_andi(DisasContext *s, DisasOps *o)
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{
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int shift = s->insn->data & 0xff;
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int size = s->insn->data >> 8;
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uint64_t mask = ((1ull << size) - 1) << shift;
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assert(!o->g_in2);
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tcg_gen_shli_i64(o->in2, o->in2, shift);
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tcg_gen_ori_i64(o->in2, o->in2, ~mask);
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tcg_gen_and_i64(o->out, o->in1, o->in2);
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/* Produce the CC from only the bits manipulated. */
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tcg_gen_andi_i64(cc_dst, o->out, mask);
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set_cc_nz_u64(s, cc_dst);
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return NO_EXIT;
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}
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static ExitStatus op_insi(DisasContext *s, DisasOps *o)
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{
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int shift = s->insn->data & 0xff;
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int size = s->insn->data >> 8;
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tcg_gen_deposit_i64(o->out, o->in1, o->in2, shift, size);
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return NO_EXIT;
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}
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static ExitStatus op_ld8s(DisasContext *s, DisasOps *o)
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{
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tcg_gen_qemu_ld8s(o->out, o->in2, get_mem_index(s));
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@ -4194,6 +4039,22 @@ static ExitStatus op_or(DisasContext *s, DisasOps *o)
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return NO_EXIT;
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}
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static ExitStatus op_ori(DisasContext *s, DisasOps *o)
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{
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int shift = s->insn->data & 0xff;
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int size = s->insn->data >> 8;
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uint64_t mask = ((1ull << size) - 1) << shift;
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assert(!o->g_in2);
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tcg_gen_shli_i64(o->in2, o->in2, shift);
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tcg_gen_or_i64(o->out, o->in1, o->in2);
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/* Produce the CC from only the bits manipulated. */
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tcg_gen_andi_i64(cc_dst, o->out, mask);
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set_cc_nz_u64(s, cc_dst);
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return NO_EXIT;
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}
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static ExitStatus op_sub(DisasContext *s, DisasOps *o)
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{
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tcg_gen_sub_i64(o->out, o->in1, o->in2);
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@ -4206,6 +4067,22 @@ static ExitStatus op_xor(DisasContext *s, DisasOps *o)
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return NO_EXIT;
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}
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static ExitStatus op_xori(DisasContext *s, DisasOps *o)
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{
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int shift = s->insn->data & 0xff;
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int size = s->insn->data >> 8;
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uint64_t mask = ((1ull << size) - 1) << shift;
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assert(!o->g_in2);
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tcg_gen_shli_i64(o->in2, o->in2, shift);
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tcg_gen_xor_i64(o->out, o->in1, o->in2);
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/* Produce the CC from only the bits manipulated. */
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tcg_gen_andi_i64(cc_dst, o->out, mask);
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set_cc_nz_u64(s, cc_dst);
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return NO_EXIT;
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}
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/* ====================================================================== */
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/* The "Cc OUTput" generators. Given the generated output (and in some cases
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the original inputs), update the various cc data structures in order to
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