mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

target-i386: Tidy cpu_regs initialization

Browse Source 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson 2013-11-06 16:38:38 +10:00
parent 8e31d234b2
commit fac0aff9f3
1 changed files with 36 additions and 51 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

87
target-i386/translate.c
View File

@ -7823,6 +7823,37 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
void optimize_flags_init(void)
{
static const char reg_names[CPU_NB_REGS][4] = {
#ifdef TARGET_X86_64
[R_EAX] = "rax",
[R_EBX] = "rbx",
[R_ECX] = "rcx",
[R_EDX] = "rdx",
[R_ESI] = "rsi",
[R_EDI] = "rdi",
[R_EBP] = "rbp",
[R_ESP] = "rsp",
[8] = "r8",
[9] = "r9",
[10] = "r10",
[11] = "r11",
[12] = "r12",
[13] = "r13",
[14] = "r14",
[15] = "r15",
#else
[R_EAX] = "eax",
[R_EBX] = "ebx",
[R_ECX] = "ecx",
[R_EDX] = "edx",
[R_ESI] = "esi",
[R_EDI] = "edi",
[R_EBP] = "ebp",
[R_ESP] = "esp",
#endif
};
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUX86State, cc_op), "cc_op");
@ -7833,57 +7864,11 @@ void optimize_flags_init(void)
cpu_cc_src2 = tcg_global_mem_new(TCG_AREG0, offsetof(CPUX86State, cc_src2),
"cc_src2");
#ifdef TARGET_X86_64
cpu_regs[R_EAX] = tcg_global_mem_new_i64(TCG_AREG0,
offsetof(CPUX86State, regs[R_EAX]), "rax");
cpu_regs[R_ECX] = tcg_global_mem_new_i64(TCG_AREG0,
offsetof(CPUX86State, regs[R_ECX]), "rcx");
cpu_regs[R_EDX] = tcg_global_mem_new_i64(TCG_AREG0,
offsetof(CPUX86State, regs[R_EDX]), "rdx");
cpu_regs[R_EBX] = tcg_global_mem_new_i64(TCG_AREG0,
offsetof(CPUX86State, regs[R_EBX]), "rbx");
cpu_regs[R_ESP] = tcg_global_mem_new_i64(TCG_AREG0,
offsetof(CPUX86State, regs[R_ESP]), "rsp");
cpu_regs[R_EBP] = tcg_global_mem_new_i64(TCG_AREG0,
offsetof(CPUX86State, regs[R_EBP]), "rbp");
cpu_regs[R_ESI] = tcg_global_mem_new_i64(TCG_AREG0,
offsetof(CPUX86State, regs[R_ESI]), "rsi");
cpu_regs[R_EDI] = tcg_global_mem_new_i64(TCG_AREG0,
offsetof(CPUX86State, regs[R_EDI]), "rdi");
cpu_regs[8] = tcg_global_mem_new_i64(TCG_AREG0,
offsetof(CPUX86State, regs[8]), "r8");
cpu_regs[9] = tcg_global_mem_new_i64(TCG_AREG0,
offsetof(CPUX86State, regs[9]), "r9");
cpu_regs[10] = tcg_global_mem_new_i64(TCG_AREG0,
offsetof(CPUX86State, regs[10]), "r10");
cpu_regs[11] = tcg_global_mem_new_i64(TCG_AREG0,
offsetof(CPUX86State, regs[11]), "r11");
cpu_regs[12] = tcg_global_mem_new_i64(TCG_AREG0,
offsetof(CPUX86State, regs[12]), "r12");
cpu_regs[13] = tcg_global_mem_new_i64(TCG_AREG0,
offsetof(CPUX86State, regs[13]), "r13");
cpu_regs[14] = tcg_global_mem_new_i64(TCG_AREG0,
offsetof(CPUX86State, regs[14]), "r14");
cpu_regs[15] = tcg_global_mem_new_i64(TCG_AREG0,
offsetof(CPUX86State, regs[15]), "r15");
#else
cpu_regs[R_EAX] = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUX86State, regs[R_EAX]), "eax");
cpu_regs[R_ECX] = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUX86State, regs[R_ECX]), "ecx");
cpu_regs[R_EDX] = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUX86State, regs[R_EDX]), "edx");
cpu_regs[R_EBX] = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUX86State, regs[R_EBX]), "ebx");
cpu_regs[R_ESP] = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUX86State, regs[R_ESP]), "esp");
cpu_regs[R_EBP] = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUX86State, regs[R_EBP]), "ebp");
cpu_regs[R_ESI] = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUX86State, regs[R_ESI]), "esi");
cpu_regs[R_EDI] = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUX86State, regs[R_EDI]), "edi");
#endif
for (i = 0; i < CPU_NB_REGS; ++i) {
cpu_regs[i] = tcg_global_mem_new(TCG_AREG0,
offsetof(CPUX86State, regs[i]),
reg_names[i]);
}
}
/* generate intermediate code in gen_opc_buf and gen_opparam_buf for