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target/mips: Add preprocessor constants for nanoMIPS

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Add ISA_NANOMIPS32 and CPU_NANOMIPS32 preprocessor constants.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
This commit is contained in:
Aleksandar Markovic 2018-08-02 16:16:01 +02:00
parent 1dfb85a875
commit fa7c0c9f5b
1 changed files with 4 additions and 0 deletions
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4
target/mips/mips-defs.h
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@ -39,6 +39,7 @@
#define ISA_MIPS64R5 0x00001000 #define ISA_MIPS64R5 0x00001000
#define ISA_MIPS32R6 0x00002000 #define ISA_MIPS32R6 0x00002000
#define ISA_MIPS64R6 0x00004000 #define ISA_MIPS64R6 0x00004000
#define ISA_NANOMIPS32 0x00008000
/* MIPS ASEs. */ /* MIPS ASEs. */
#define ASE_MIPS16 0x00010000 #define ASE_MIPS16 0x00010000
@ -87,6 +88,9 @@
#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6) #define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6)
#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6) #define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6)
/* Wave Computing: "nanoMIPS" */
#define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32)
/* Strictly follow the architecture standard: /* Strictly follow the architecture standard:
- Disallow "special" instruction handling for PMON/SPIM. - Disallow "special" instruction handling for PMON/SPIM.
Note that we still maintain Count/Compare to match the host clock. */ Note that we still maintain Count/Compare to match the host clock. */