mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

target-i386: Rename struct XMMReg to ZMMReg

Browse Source 
The struct represents a 512-bit register, so name it accordingly.

This is just a global search+replace, no other changes are being
introduced.

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
This commit is contained in:
Eduardo Habkost 2015-11-19 16:12:40 -02:00
parent 9618f40f06
commit fa4518741e
5 changed files with 115 additions and 115 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
target-i386/cpu.h
View File

@ -732,7 +732,7 @@ typedef union {
uint64_t _q[8]; uint64_t _q[8];
float32 _s[16]; float32 _s[16];
float64 _d[8]; float64 _d[8];
} XMMReg; /* really zmm */ } ZMMReg;
typedef union { typedef union {
uint8_t _b[8]; uint8_t _b[8];
@ -865,8 +865,8 @@ typedef struct CPUX86State {
float_status mmx_status; /* for 3DNow! float ops */ float_status mmx_status; /* for 3DNow! float ops */
float_status sse_status; float_status sse_status;
uint32_t mxcsr; uint32_t mxcsr;
XMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32]; ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32];
XMMReg xmm_t0; ZMMReg xmm_t0;
MMXReg mmx_t0; MMXReg mmx_t0;
uint64_t opmask_regs[NB_OPMASK_REGS]; uint64_t opmask_regs[NB_OPMASK_REGS];

40
target-i386/machine.c
View File

@ -36,15 +36,15 @@ static const VMStateDescription vmstate_xmm_reg = {
.version_id = 1, .version_id = 1,
.minimum_version_id = 1, .minimum_version_id = 1,
.fields = (VMStateField[]) { .fields = (VMStateField[]) {
VMSTATE_UINT64(XMM_Q(0), XMMReg), VMSTATE_UINT64(XMM_Q(0), ZMMReg),
VMSTATE_UINT64(XMM_Q(1), XMMReg), VMSTATE_UINT64(XMM_Q(1), ZMMReg),
VMSTATE_END_OF_LIST() VMSTATE_END_OF_LIST()
} }
}; };
#define VMSTATE_XMM_REGS(_field, _state, _start) \ #define VMSTATE_XMM_REGS(_field, _state, _start) \
VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0, \ VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0, \
vmstate_xmm_reg, XMMReg) vmstate_xmm_reg, ZMMReg)
/* YMMH format is the same as XMM, but for bits 128-255 */ /* YMMH format is the same as XMM, but for bits 128-255 */
static const VMStateDescription vmstate_ymmh_reg = { static const VMStateDescription vmstate_ymmh_reg = {
@ -52,32 +52,32 @@ static const VMStateDescription vmstate_ymmh_reg = {
.version_id = 1, .version_id = 1,
.minimum_version_id = 1, .minimum_version_id = 1,
.fields = (VMStateField[]) { .fields = (VMStateField[]) {
VMSTATE_UINT64(XMM_Q(2), XMMReg), VMSTATE_UINT64(XMM_Q(2), ZMMReg),
VMSTATE_UINT64(XMM_Q(3), XMMReg), VMSTATE_UINT64(XMM_Q(3), ZMMReg),
VMSTATE_END_OF_LIST() VMSTATE_END_OF_LIST()
} }
}; };
#define VMSTATE_YMMH_REGS_VARS(_field, _state, _start, _v) \ #define VMSTATE_YMMH_REGS_VARS(_field, _state, _start, _v) \
VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, _v, \ VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, _v, \
vmstate_ymmh_reg, XMMReg) vmstate_ymmh_reg, ZMMReg)
static const VMStateDescription vmstate_zmmh_reg = { static const VMStateDescription vmstate_zmmh_reg = {
.name = "zmmh_reg", .name = "zmmh_reg",
.version_id = 1, .version_id = 1,
.minimum_version_id = 1, .minimum_version_id = 1,
.fields = (VMStateField[]) { .fields = (VMStateField[]) {
VMSTATE_UINT64(XMM_Q(4), XMMReg), VMSTATE_UINT64(XMM_Q(4), ZMMReg),
VMSTATE_UINT64(XMM_Q(5), XMMReg), VMSTATE_UINT64(XMM_Q(5), ZMMReg),
VMSTATE_UINT64(XMM_Q(6), XMMReg), VMSTATE_UINT64(XMM_Q(6), ZMMReg),
VMSTATE_UINT64(XMM_Q(7), XMMReg), VMSTATE_UINT64(XMM_Q(7), ZMMReg),
VMSTATE_END_OF_LIST() VMSTATE_END_OF_LIST()
} }
}; };
#define VMSTATE_ZMMH_REGS_VARS(_field, _state, _start) \ #define VMSTATE_ZMMH_REGS_VARS(_field, _state, _start) \
VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0, \ VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0, \
vmstate_zmmh_reg, XMMReg) vmstate_zmmh_reg, ZMMReg)
#ifdef TARGET_X86_64 #ifdef TARGET_X86_64
static const VMStateDescription vmstate_hi16_zmm_reg = { static const VMStateDescription vmstate_hi16_zmm_reg = {
@ -85,21 +85,21 @@ static const VMStateDescription vmstate_hi16_zmm_reg = {
.version_id = 1, .version_id = 1,
.minimum_version_id = 1, .minimum_version_id = 1,
.fields = (VMStateField[]) { .fields = (VMStateField[]) {
VMSTATE_UINT64(XMM_Q(0), XMMReg), VMSTATE_UINT64(XMM_Q(0), ZMMReg),
VMSTATE_UINT64(XMM_Q(1), XMMReg), VMSTATE_UINT64(XMM_Q(1), ZMMReg),
VMSTATE_UINT64(XMM_Q(2), XMMReg), VMSTATE_UINT64(XMM_Q(2), ZMMReg),
VMSTATE_UINT64(XMM_Q(3), XMMReg), VMSTATE_UINT64(XMM_Q(3), ZMMReg),
VMSTATE_UINT64(XMM_Q(4), XMMReg), VMSTATE_UINT64(XMM_Q(4), ZMMReg),
VMSTATE_UINT64(XMM_Q(5), XMMReg), VMSTATE_UINT64(XMM_Q(5), ZMMReg),
VMSTATE_UINT64(XMM_Q(6), XMMReg), VMSTATE_UINT64(XMM_Q(6), ZMMReg),
VMSTATE_UINT64(XMM_Q(7), XMMReg), VMSTATE_UINT64(XMM_Q(7), ZMMReg),
VMSTATE_END_OF_LIST() VMSTATE_END_OF_LIST()
} }
}; };
#define VMSTATE_Hi16_ZMM_REGS_VARS(_field, _state, _start) \ #define VMSTATE_Hi16_ZMM_REGS_VARS(_field, _state, _start) \
VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0, \ VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0, \
vmstate_hi16_zmm_reg, XMMReg) vmstate_hi16_zmm_reg, ZMMReg)
#endif #endif
static const VMStateDescription vmstate_bnd_regs = { static const VMStateDescription vmstate_bnd_regs = {

82
target-i386/ops_sse.h
View File

@ -29,7 +29,7 @@
#define Q(n) MMX_Q(n) #define Q(n) MMX_Q(n)
#define SUFFIX _mmx #define SUFFIX _mmx
#else #else
#define Reg XMMReg #define Reg ZMMReg
#define XMM_ONLY(...) __VA_ARGS__ #define XMM_ONLY(...) __VA_ARGS__
#define B(n) XMM_B(n) #define B(n) XMM_B(n)
#define W(n) XMM_W(n) #define W(n) XMM_W(n)
@ -675,42 +675,42 @@ void helper_cvtdq2pd(CPUX86State *env, Reg *d, Reg *s)
d->XMM_D(1) = int32_to_float64(l1, &env->sse_status); d->XMM_D(1) = int32_to_float64(l1, &env->sse_status);
} }
void helper_cvtpi2ps(CPUX86State *env, XMMReg *d, MMXReg *s) void helper_cvtpi2ps(CPUX86State *env, ZMMReg *d, MMXReg *s)
{ {
d->XMM_S(0) = int32_to_float32(s->MMX_L(0), &env->sse_status); d->XMM_S(0) = int32_to_float32(s->MMX_L(0), &env->sse_status);
d->XMM_S(1) = int32_to_float32(s->MMX_L(1), &env->sse_status); d->XMM_S(1) = int32_to_float32(s->MMX_L(1), &env->sse_status);
} }
void helper_cvtpi2pd(CPUX86State *env, XMMReg *d, MMXReg *s) void helper_cvtpi2pd(CPUX86State *env, ZMMReg *d, MMXReg *s)
{ {
d->XMM_D(0) = int32_to_float64(s->MMX_L(0), &env->sse_status); d->XMM_D(0) = int32_to_float64(s->MMX_L(0), &env->sse_status);
d->XMM_D(1) = int32_to_float64(s->MMX_L(1), &env->sse_status); d->XMM_D(1) = int32_to_float64(s->MMX_L(1), &env->sse_status);
} }
void helper_cvtsi2ss(CPUX86State *env, XMMReg *d, uint32_t val) void helper_cvtsi2ss(CPUX86State *env, ZMMReg *d, uint32_t val)
{ {
d->XMM_S(0) = int32_to_float32(val, &env->sse_status); d->XMM_S(0) = int32_to_float32(val, &env->sse_status);
} }
void helper_cvtsi2sd(CPUX86State *env, XMMReg *d, uint32_t val) void helper_cvtsi2sd(CPUX86State *env, ZMMReg *d, uint32_t val)
{ {
d->XMM_D(0) = int32_to_float64(val, &env->sse_status); d->XMM_D(0) = int32_to_float64(val, &env->sse_status);
} }
#ifdef TARGET_X86_64 #ifdef TARGET_X86_64
void helper_cvtsq2ss(CPUX86State *env, XMMReg *d, uint64_t val) void helper_cvtsq2ss(CPUX86State *env, ZMMReg *d, uint64_t val)
{ {
d->XMM_S(0) = int64_to_float32(val, &env->sse_status); d->XMM_S(0) = int64_to_float32(val, &env->sse_status);
} }
void helper_cvtsq2sd(CPUX86State *env, XMMReg *d, uint64_t val) void helper_cvtsq2sd(CPUX86State *env, ZMMReg *d, uint64_t val)
{ {
d->XMM_D(0) = int64_to_float64(val, &env->sse_status); d->XMM_D(0) = int64_to_float64(val, &env->sse_status);
} }
#endif #endif
/* float to integer */ /* float to integer */
void helper_cvtps2dq(CPUX86State *env, XMMReg *d, XMMReg *s) void helper_cvtps2dq(CPUX86State *env, ZMMReg *d, ZMMReg *s)
{ {
d->XMM_L(0) = float32_to_int32(s->XMM_S(0), &env->sse_status); d->XMM_L(0) = float32_to_int32(s->XMM_S(0), &env->sse_status);
d->XMM_L(1) = float32_to_int32(s->XMM_S(1), &env->sse_status); d->XMM_L(1) = float32_to_int32(s->XMM_S(1), &env->sse_status);
@ -718,49 +718,49 @@ void helper_cvtps2dq(CPUX86State *env, XMMReg *d, XMMReg *s)
d->XMM_L(3) = float32_to_int32(s->XMM_S(3), &env->sse_status); d->XMM_L(3) = float32_to_int32(s->XMM_S(3), &env->sse_status);
} }
void helper_cvtpd2dq(CPUX86State *env, XMMReg *d, XMMReg *s) void helper_cvtpd2dq(CPUX86State *env, ZMMReg *d, ZMMReg *s)
{ {
d->XMM_L(0) = float64_to_int32(s->XMM_D(0), &env->sse_status); d->XMM_L(0) = float64_to_int32(s->XMM_D(0), &env->sse_status);
d->XMM_L(1) = float64_to_int32(s->XMM_D(1), &env->sse_status); d->XMM_L(1) = float64_to_int32(s->XMM_D(1), &env->sse_status);
d->XMM_Q(1) = 0; d->XMM_Q(1) = 0;
} }
void helper_cvtps2pi(CPUX86State *env, MMXReg *d, XMMReg *s) void helper_cvtps2pi(CPUX86State *env, MMXReg *d, ZMMReg *s)
{ {
d->MMX_L(0) = float32_to_int32(s->XMM_S(0), &env->sse_status); d->MMX_L(0) = float32_to_int32(s->XMM_S(0), &env->sse_status);
d->MMX_L(1) = float32_to_int32(s->XMM_S(1), &env->sse_status); d->MMX_L(1) = float32_to_int32(s->XMM_S(1), &env->sse_status);
} }
void helper_cvtpd2pi(CPUX86State *env, MMXReg *d, XMMReg *s) void helper_cvtpd2pi(CPUX86State *env, MMXReg *d, ZMMReg *s)
{ {
d->MMX_L(0) = float64_to_int32(s->XMM_D(0), &env->sse_status); d->MMX_L(0) = float64_to_int32(s->XMM_D(0), &env->sse_status);
d->MMX_L(1) = float64_to_int32(s->XMM_D(1), &env->sse_status); d->MMX_L(1) = float64_to_int32(s->XMM_D(1), &env->sse_status);
} }
int32_t helper_cvtss2si(CPUX86State *env, XMMReg *s) int32_t helper_cvtss2si(CPUX86State *env, ZMMReg *s)
{ {
return float32_to_int32(s->XMM_S(0), &env->sse_status); return float32_to_int32(s->XMM_S(0), &env->sse_status);
} }
int32_t helper_cvtsd2si(CPUX86State *env, XMMReg *s) int32_t helper_cvtsd2si(CPUX86State *env, ZMMReg *s)
{ {
return float64_to_int32(s->XMM_D(0), &env->sse_status); return float64_to_int32(s->XMM_D(0), &env->sse_status);
} }
#ifdef TARGET_X86_64 #ifdef TARGET_X86_64
int64_t helper_cvtss2sq(CPUX86State *env, XMMReg *s) int64_t helper_cvtss2sq(CPUX86State *env, ZMMReg *s)
{ {
return float32_to_int64(s->XMM_S(0), &env->sse_status); return float32_to_int64(s->XMM_S(0), &env->sse_status);
} }
int64_t helper_cvtsd2sq(CPUX86State *env, XMMReg *s) int64_t helper_cvtsd2sq(CPUX86State *env, ZMMReg *s)
{ {
return float64_to_int64(s->XMM_D(0), &env->sse_status); return float64_to_int64(s->XMM_D(0), &env->sse_status);
} }
#endif #endif
/* float to integer truncated */ /* float to integer truncated */
void helper_cvttps2dq(CPUX86State *env, XMMReg *d, XMMReg *s) void helper_cvttps2dq(CPUX86State *env, ZMMReg *d, ZMMReg *s)
{ {
d->XMM_L(0) = float32_to_int32_round_to_zero(s->XMM_S(0), &env->sse_status); d->XMM_L(0) = float32_to_int32_round_to_zero(s->XMM_S(0), &env->sse_status);
d->XMM_L(1) = float32_to_int32_round_to_zero(s->XMM_S(1), &env->sse_status); d->XMM_L(1) = float32_to_int32_round_to_zero(s->XMM_S(1), &env->sse_status);
@ -768,48 +768,48 @@ void helper_cvttps2dq(CPUX86State *env, XMMReg *d, XMMReg *s)
d->XMM_L(3) = float32_to_int32_round_to_zero(s->XMM_S(3), &env->sse_status); d->XMM_L(3) = float32_to_int32_round_to_zero(s->XMM_S(3), &env->sse_status);
} }
void helper_cvttpd2dq(CPUX86State *env, XMMReg *d, XMMReg *s) void helper_cvttpd2dq(CPUX86State *env, ZMMReg *d, ZMMReg *s)
{ {
d->XMM_L(0) = float64_to_int32_round_to_zero(s->XMM_D(0), &env->sse_status); d->XMM_L(0) = float64_to_int32_round_to_zero(s->XMM_D(0), &env->sse_status);
d->XMM_L(1) = float64_to_int32_round_to_zero(s->XMM_D(1), &env->sse_status); d->XMM_L(1) = float64_to_int32_round_to_zero(s->XMM_D(1), &env->sse_status);
d->XMM_Q(1) = 0; d->XMM_Q(1) = 0;
} }
void helper_cvttps2pi(CPUX86State *env, MMXReg *d, XMMReg *s) void helper_cvttps2pi(CPUX86State *env, MMXReg *d, ZMMReg *s)
{ {
d->MMX_L(0) = float32_to_int32_round_to_zero(s->XMM_S(0), &env->sse_status); d->MMX_L(0) = float32_to_int32_round_to_zero(s->XMM_S(0), &env->sse_status);
d->MMX_L(1) = float32_to_int32_round_to_zero(s->XMM_S(1), &env->sse_status); d->MMX_L(1) = float32_to_int32_round_to_zero(s->XMM_S(1), &env->sse_status);
} }
void helper_cvttpd2pi(CPUX86State *env, MMXReg *d, XMMReg *s) void helper_cvttpd2pi(CPUX86State *env, MMXReg *d, ZMMReg *s)
{ {
d->MMX_L(0) = float64_to_int32_round_to_zero(s->XMM_D(0), &env->sse_status); d->MMX_L(0) = float64_to_int32_round_to_zero(s->XMM_D(0), &env->sse_status);
d->MMX_L(1) = float64_to_int32_round_to_zero(s->XMM_D(1), &env->sse_status); d->MMX_L(1) = float64_to_int32_round_to_zero(s->XMM_D(1), &env->sse_status);
} }
int32_t helper_cvttss2si(CPUX86State *env, XMMReg *s) int32_t helper_cvttss2si(CPUX86State *env, ZMMReg *s)
{ {
return float32_to_int32_round_to_zero(s->XMM_S(0), &env->sse_status); return float32_to_int32_round_to_zero(s->XMM_S(0), &env->sse_status);
} }
int32_t helper_cvttsd2si(CPUX86State *env, XMMReg *s) int32_t helper_cvttsd2si(CPUX86State *env, ZMMReg *s)
{ {
return float64_to_int32_round_to_zero(s->XMM_D(0), &env->sse_status); return float64_to_int32_round_to_zero(s->XMM_D(0), &env->sse_status);
} }
#ifdef TARGET_X86_64 #ifdef TARGET_X86_64
int64_t helper_cvttss2sq(CPUX86State *env, XMMReg *s) int64_t helper_cvttss2sq(CPUX86State *env, ZMMReg *s)
{ {
return float32_to_int64_round_to_zero(s->XMM_S(0), &env->sse_status); return float32_to_int64_round_to_zero(s->XMM_S(0), &env->sse_status);
} }
int64_t helper_cvttsd2sq(CPUX86State *env, XMMReg *s) int64_t helper_cvttsd2sq(CPUX86State *env, ZMMReg *s)
{ {
return float64_to_int64_round_to_zero(s->XMM_D(0), &env->sse_status); return float64_to_int64_round_to_zero(s->XMM_D(0), &env->sse_status);
} }
#endif #endif
void helper_rsqrtps(CPUX86State *env, XMMReg *d, XMMReg *s) void helper_rsqrtps(CPUX86State *env, ZMMReg *d, ZMMReg *s)
{ {
d->XMM_S(0) = float32_div(float32_one, d->XMM_S(0) = float32_div(float32_one,
float32_sqrt(s->XMM_S(0), &env->sse_status), float32_sqrt(s->XMM_S(0), &env->sse_status),
@ -825,14 +825,14 @@ void helper_rsqrtps(CPUX86State *env, XMMReg *d, XMMReg *s)
&env->sse_status); &env->sse_status);
} }
void helper_rsqrtss(CPUX86State *env, XMMReg *d, XMMReg *s) void helper_rsqrtss(CPUX86State *env, ZMMReg *d, ZMMReg *s)
{ {
d->XMM_S(0) = float32_div(float32_one, d->XMM_S(0) = float32_div(float32_one,
float32_sqrt(s->XMM_S(0), &env->sse_status), float32_sqrt(s->XMM_S(0), &env->sse_status),
&env->sse_status); &env->sse_status);
} }
void helper_rcpps(CPUX86State *env, XMMReg *d, XMMReg *s) void helper_rcpps(CPUX86State *env, ZMMReg *d, ZMMReg *s)
{ {
d->XMM_S(0) = float32_div(float32_one, s->XMM_S(0), &env->sse_status); d->XMM_S(0) = float32_div(float32_one, s->XMM_S(0), &env->sse_status);
d->XMM_S(1) = float32_div(float32_one, s->XMM_S(1), &env->sse_status); d->XMM_S(1) = float32_div(float32_one, s->XMM_S(1), &env->sse_status);
@ -840,7 +840,7 @@ void helper_rcpps(CPUX86State *env, XMMReg *d, XMMReg *s)
d->XMM_S(3) = float32_div(float32_one, s->XMM_S(3), &env->sse_status); d->XMM_S(3) = float32_div(float32_one, s->XMM_S(3), &env->sse_status);
} }
void helper_rcpss(CPUX86State *env, XMMReg *d, XMMReg *s) void helper_rcpss(CPUX86State *env, ZMMReg *d, ZMMReg *s)
{ {
d->XMM_S(0) = float32_div(float32_one, s->XMM_S(0), &env->sse_status); d->XMM_S(0) = float32_div(float32_one, s->XMM_S(0), &env->sse_status);
} }
@ -857,12 +857,12 @@ static inline uint64_t helper_extrq(uint64_t src, int shift, int len)
return (src >> shift) & mask; return (src >> shift) & mask;
} }
void helper_extrq_r(CPUX86State *env, XMMReg *d, XMMReg *s) void helper_extrq_r(CPUX86State *env, ZMMReg *d, ZMMReg *s)
{ {
d->XMM_Q(0) = helper_extrq(d->XMM_Q(0), s->XMM_B(1), s->XMM_B(0)); d->XMM_Q(0) = helper_extrq(d->XMM_Q(0), s->XMM_B(1), s->XMM_B(0));
} }
void helper_extrq_i(CPUX86State *env, XMMReg *d, int index, int length) void helper_extrq_i(CPUX86State *env, ZMMReg *d, int index, int length)
{ {
d->XMM_Q(0) = helper_extrq(d->XMM_Q(0), index, length); d->XMM_Q(0) = helper_extrq(d->XMM_Q(0), index, length);
} }
@ -879,19 +879,19 @@ static inline uint64_t helper_insertq(uint64_t src, int shift, int len)
return (src & ~(mask << shift)) | ((src & mask) << shift); return (src & ~(mask << shift)) | ((src & mask) << shift);
} }
void helper_insertq_r(CPUX86State *env, XMMReg *d, XMMReg *s) void helper_insertq_r(CPUX86State *env, ZMMReg *d, ZMMReg *s)
{ {
d->XMM_Q(0) = helper_insertq(s->XMM_Q(0), s->XMM_B(9), s->XMM_B(8)); d->XMM_Q(0) = helper_insertq(s->XMM_Q(0), s->XMM_B(9), s->XMM_B(8));
} }
void helper_insertq_i(CPUX86State *env, XMMReg *d, int index, int length) void helper_insertq_i(CPUX86State *env, ZMMReg *d, int index, int length)
{ {
d->XMM_Q(0) = helper_insertq(d->XMM_Q(0), index, length); d->XMM_Q(0) = helper_insertq(d->XMM_Q(0), index, length);
} }
void helper_haddps(CPUX86State *env, XMMReg *d, XMMReg *s) void helper_haddps(CPUX86State *env, ZMMReg *d, ZMMReg *s)
{ {
XMMReg r; ZMMReg r;
r.XMM_S(0) = float32_add(d->XMM_S(0), d->XMM_S(1), &env->sse_status); r.XMM_S(0) = float32_add(d->XMM_S(0), d->XMM_S(1), &env->sse_status);
r.XMM_S(1) = float32_add(d->XMM_S(2), d->XMM_S(3), &env->sse_status); r.XMM_S(1) = float32_add(d->XMM_S(2), d->XMM_S(3), &env->sse_status);
@ -900,18 +900,18 @@ void helper_haddps(CPUX86State *env, XMMReg *d, XMMReg *s)
*d = r; *d = r;
} }
void helper_haddpd(CPUX86State *env, XMMReg *d, XMMReg *s) void helper_haddpd(CPUX86State *env, ZMMReg *d, ZMMReg *s)
{ {
XMMReg r; ZMMReg r;
r.XMM_D(0) = float64_add(d->XMM_D(0), d->XMM_D(1), &env->sse_status); r.XMM_D(0) = float64_add(d->XMM_D(0), d->XMM_D(1), &env->sse_status);
r.XMM_D(1) = float64_add(s->XMM_D(0), s->XMM_D(1), &env->sse_status); r.XMM_D(1) = float64_add(s->XMM_D(0), s->XMM_D(1), &env->sse_status);
*d = r; *d = r;
} }
void helper_hsubps(CPUX86State *env, XMMReg *d, XMMReg *s) void helper_hsubps(CPUX86State *env, ZMMReg *d, ZMMReg *s)
{ {
XMMReg r; ZMMReg r;
r.XMM_S(0) = float32_sub(d->XMM_S(0), d->XMM_S(1), &env->sse_status); r.XMM_S(0) = float32_sub(d->XMM_S(0), d->XMM_S(1), &env->sse_status);
r.XMM_S(1) = float32_sub(d->XMM_S(2), d->XMM_S(3), &env->sse_status); r.XMM_S(1) = float32_sub(d->XMM_S(2), d->XMM_S(3), &env->sse_status);
@ -920,16 +920,16 @@ void helper_hsubps(CPUX86State *env, XMMReg *d, XMMReg *s)
*d = r; *d = r;
} }
void helper_hsubpd(CPUX86State *env, XMMReg *d, XMMReg *s) void helper_hsubpd(CPUX86State *env, ZMMReg *d, ZMMReg *s)
{ {
XMMReg r; ZMMReg r;
r.XMM_D(0) = float64_sub(d->XMM_D(0), d->XMM_D(1), &env->sse_status); r.XMM_D(0) = float64_sub(d->XMM_D(0), d->XMM_D(1), &env->sse_status);
r.XMM_D(1) = float64_sub(s->XMM_D(0), s->XMM_D(1), &env->sse_status); r.XMM_D(1) = float64_sub(s->XMM_D(0), s->XMM_D(1), &env->sse_status);
*d = r; *d = r;
} }
void helper_addsubps(CPUX86State *env, XMMReg *d, XMMReg *s) void helper_addsubps(CPUX86State *env, ZMMReg *d, ZMMReg *s)
{ {
d->XMM_S(0) = float32_sub(d->XMM_S(0), s->XMM_S(0), &env->sse_status); d->XMM_S(0) = float32_sub(d->XMM_S(0), s->XMM_S(0), &env->sse_status);
d->XMM_S(1) = float32_add(d->XMM_S(1), s->XMM_S(1), &env->sse_status); d->XMM_S(1) = float32_add(d->XMM_S(1), s->XMM_S(1), &env->sse_status);
@ -937,7 +937,7 @@ void helper_addsubps(CPUX86State *env, XMMReg *d, XMMReg *s)
d->XMM_S(3) = float32_add(d->XMM_S(3), s->XMM_S(3), &env->sse_status); d->XMM_S(3) = float32_add(d->XMM_S(3), s->XMM_S(3), &env->sse_status);
} }
void helper_addsubpd(CPUX86State *env, XMMReg *d, XMMReg *s) void helper_addsubpd(CPUX86State *env, ZMMReg *d, ZMMReg *s)
{ {
d->XMM_D(0) = float64_sub(d->XMM_D(0), s->XMM_D(0), &env->sse_status); d->XMM_D(0) = float64_sub(d->XMM_D(0), s->XMM_D(0), &env->sse_status);
d->XMM_D(1) = float64_add(d->XMM_D(1), s->XMM_D(1), &env->sse_status); d->XMM_D(1) = float64_add(d->XMM_D(1), s->XMM_D(1), &env->sse_status);

80
target-i386/ops_sse_header.h
View File

@ -20,18 +20,18 @@
#define Reg MMXReg #define Reg MMXReg
#define SUFFIX _mmx #define SUFFIX _mmx
#else #else
#define Reg XMMReg #define Reg ZMMReg
#define SUFFIX _xmm #define SUFFIX _xmm
#endif #endif
#define dh_alias_Reg ptr #define dh_alias_Reg ptr
#define dh_alias_XMMReg ptr #define dh_alias_ZMMReg ptr
#define dh_alias_MMXReg ptr #define dh_alias_MMXReg ptr
#define dh_ctype_Reg Reg * #define dh_ctype_Reg Reg *
#define dh_ctype_XMMReg XMMReg * #define dh_ctype_ZMMReg ZMMReg *
#define dh_ctype_MMXReg MMXReg * #define dh_ctype_MMXReg MMXReg *
#define dh_is_signed_Reg dh_is_signed_ptr #define dh_is_signed_Reg dh_is_signed_ptr
#define dh_is_signed_XMMReg dh_is_signed_ptr #define dh_is_signed_ZMMReg dh_is_signed_ptr
#define dh_is_signed_MMXReg dh_is_signed_ptr #define dh_is_signed_MMXReg dh_is_signed_ptr
DEF_HELPER_3(glue(psrlw, SUFFIX), void, env, Reg, Reg) DEF_HELPER_3(glue(psrlw, SUFFIX), void, env, Reg, Reg)
@ -154,52 +154,52 @@ DEF_HELPER_3(cvtss2sd, void, env, Reg, Reg)
DEF_HELPER_3(cvtsd2ss, void, env, Reg, Reg) DEF_HELPER_3(cvtsd2ss, void, env, Reg, Reg)
DEF_HELPER_3(cvtdq2ps, void, env, Reg, Reg) DEF_HELPER_3(cvtdq2ps, void, env, Reg, Reg)
DEF_HELPER_3(cvtdq2pd, void, env, Reg, Reg) DEF_HELPER_3(cvtdq2pd, void, env, Reg, Reg)
DEF_HELPER_3(cvtpi2ps, void, env, XMMReg, MMXReg) DEF_HELPER_3(cvtpi2ps, void, env, ZMMReg, MMXReg)
DEF_HELPER_3(cvtpi2pd, void, env, XMMReg, MMXReg) DEF_HELPER_3(cvtpi2pd, void, env, ZMMReg, MMXReg)
DEF_HELPER_3(cvtsi2ss, void, env, XMMReg, i32) DEF_HELPER_3(cvtsi2ss, void, env, ZMMReg, i32)
DEF_HELPER_3(cvtsi2sd, void, env, XMMReg, i32) DEF_HELPER_3(cvtsi2sd, void, env, ZMMReg, i32)
#ifdef TARGET_X86_64 #ifdef TARGET_X86_64
DEF_HELPER_3(cvtsq2ss, void, env, XMMReg, i64) DEF_HELPER_3(cvtsq2ss, void, env, ZMMReg, i64)
DEF_HELPER_3(cvtsq2sd, void, env, XMMReg, i64) DEF_HELPER_3(cvtsq2sd, void, env, ZMMReg, i64)
#endif #endif
DEF_HELPER_3(cvtps2dq, void, env, XMMReg, XMMReg) DEF_HELPER_3(cvtps2dq, void, env, ZMMReg, ZMMReg)
DEF_HELPER_3(cvtpd2dq, void, env, XMMReg, XMMReg) DEF_HELPER_3(cvtpd2dq, void, env, ZMMReg, ZMMReg)
DEF_HELPER_3(cvtps2pi, void, env, MMXReg, XMMReg) DEF_HELPER_3(cvtps2pi, void, env, MMXReg, ZMMReg)
DEF_HELPER_3(cvtpd2pi, void, env, MMXReg, XMMReg) DEF_HELPER_3(cvtpd2pi, void, env, MMXReg, ZMMReg)
DEF_HELPER_2(cvtss2si, s32, env, XMMReg) DEF_HELPER_2(cvtss2si, s32, env, ZMMReg)
DEF_HELPER_2(cvtsd2si, s32, env, XMMReg) DEF_HELPER_2(cvtsd2si, s32, env, ZMMReg)
#ifdef TARGET_X86_64 #ifdef TARGET_X86_64
DEF_HELPER_2(cvtss2sq, s64, env, XMMReg) DEF_HELPER_2(cvtss2sq, s64, env, ZMMReg)
DEF_HELPER_2(cvtsd2sq, s64, env, XMMReg) DEF_HELPER_2(cvtsd2sq, s64, env, ZMMReg)
#endif #endif
DEF_HELPER_3(cvttps2dq, void, env, XMMReg, XMMReg) DEF_HELPER_3(cvttps2dq, void, env, ZMMReg, ZMMReg)
DEF_HELPER_3(cvttpd2dq, void, env, XMMReg, XMMReg) DEF_HELPER_3(cvttpd2dq, void, env, ZMMReg, ZMMReg)
DEF_HELPER_3(cvttps2pi, void, env, MMXReg, XMMReg) DEF_HELPER_3(cvttps2pi, void, env, MMXReg, ZMMReg)
DEF_HELPER_3(cvttpd2pi, void, env, MMXReg, XMMReg) DEF_HELPER_3(cvttpd2pi, void, env, MMXReg, ZMMReg)
DEF_HELPER_2(cvttss2si, s32, env, XMMReg) DEF_HELPER_2(cvttss2si, s32, env, ZMMReg)
DEF_HELPER_2(cvttsd2si, s32, env, XMMReg) DEF_HELPER_2(cvttsd2si, s32, env, ZMMReg)
#ifdef TARGET_X86_64 #ifdef TARGET_X86_64
DEF_HELPER_2(cvttss2sq, s64, env, XMMReg) DEF_HELPER_2(cvttss2sq, s64, env, ZMMReg)
DEF_HELPER_2(cvttsd2sq, s64, env, XMMReg) DEF_HELPER_2(cvttsd2sq, s64, env, ZMMReg)
#endif #endif
DEF_HELPER_3(rsqrtps, void, env, XMMReg, XMMReg) DEF_HELPER_3(rsqrtps, void, env, ZMMReg, ZMMReg)
DEF_HELPER_3(rsqrtss, void, env, XMMReg, XMMReg) DEF_HELPER_3(rsqrtss, void, env, ZMMReg, ZMMReg)
DEF_HELPER_3(rcpps, void, env, XMMReg, XMMReg) DEF_HELPER_3(rcpps, void, env, ZMMReg, ZMMReg)
DEF_HELPER_3(rcpss, void, env, XMMReg, XMMReg) DEF_HELPER_3(rcpss, void, env, ZMMReg, ZMMReg)
DEF_HELPER_3(extrq_r, void, env, XMMReg, XMMReg) DEF_HELPER_3(extrq_r, void, env, ZMMReg, ZMMReg)
DEF_HELPER_4(extrq_i, void, env, XMMReg, int, int) DEF_HELPER_4(extrq_i, void, env, ZMMReg, int, int)
DEF_HELPER_3(insertq_r, void, env, XMMReg, XMMReg) DEF_HELPER_3(insertq_r, void, env, ZMMReg, ZMMReg)
DEF_HELPER_4(insertq_i, void, env, XMMReg, int, int) DEF_HELPER_4(insertq_i, void, env, ZMMReg, int, int)
DEF_HELPER_3(haddps, void, env, XMMReg, XMMReg) DEF_HELPER_3(haddps, void, env, ZMMReg, ZMMReg)
DEF_HELPER_3(haddpd, void, env, XMMReg, XMMReg) DEF_HELPER_3(haddpd, void, env, ZMMReg, ZMMReg)
DEF_HELPER_3(hsubps, void, env, XMMReg, XMMReg) DEF_HELPER_3(hsubps, void, env, ZMMReg, ZMMReg)
DEF_HELPER_3(hsubpd, void, env, XMMReg, XMMReg) DEF_HELPER_3(hsubpd, void, env, ZMMReg, ZMMReg)
DEF_HELPER_3(addsubps, void, env, XMMReg, XMMReg) DEF_HELPER_3(addsubps, void, env, ZMMReg, ZMMReg)
DEF_HELPER_3(addsubpd, void, env, XMMReg, XMMReg) DEF_HELPER_3(addsubpd, void, env, ZMMReg, ZMMReg)
#define SSE_HELPER_CMP(name, F) \ #define SSE_HELPER_CMP(name, F) \
DEF_HELPER_3(name ## ps, void, env, Reg, Reg) \ DEF_HELPER_3(name ## ps, void, env, Reg, Reg) \

22
target-i386/translate.c
View File

@ -2602,28 +2602,28 @@ static inline void gen_ldo_env_A0(DisasContext *s, int offset)
{ {
int mem_index = s->mem_index; int mem_index = s->mem_index;
tcg_gen_qemu_ld_i64(cpu_tmp1_i64, cpu_A0, mem_index, MO_LEQ); tcg_gen_qemu_ld_i64(cpu_tmp1_i64, cpu_A0, mem_index, MO_LEQ);
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0))); tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(ZMMReg, XMM_Q(0)));
tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8); tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
tcg_gen_qemu_ld_i64(cpu_tmp1_i64, cpu_tmp0, mem_index, MO_LEQ); tcg_gen_qemu_ld_i64(cpu_tmp1_i64, cpu_tmp0, mem_index, MO_LEQ);
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1))); tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(ZMMReg, XMM_Q(1)));
} }
static inline void gen_sto_env_A0(DisasContext *s, int offset) static inline void gen_sto_env_A0(DisasContext *s, int offset)
{ {
int mem_index = s->mem_index; int mem_index = s->mem_index;
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0))); tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(ZMMReg, XMM_Q(0)));
tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_A0, mem_index, MO_LEQ); tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_A0, mem_index, MO_LEQ);
tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8); tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1))); tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(ZMMReg, XMM_Q(1)));
tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_tmp0, mem_index, MO_LEQ); tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_tmp0, mem_index, MO_LEQ);
} }
static inline void gen_op_movo(int d_offset, int s_offset) static inline void gen_op_movo(int d_offset, int s_offset)
{ {
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset + offsetof(XMMReg, XMM_Q(0))); tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset + offsetof(ZMMReg, XMM_Q(0)));
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset + offsetof(XMMReg, XMM_Q(0))); tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset + offsetof(ZMMReg, XMM_Q(0)));
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset + offsetof(XMMReg, XMM_Q(1))); tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset + offsetof(ZMMReg, XMM_Q(1)));
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset + offsetof(XMMReg, XMM_Q(1))); tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset + offsetof(ZMMReg, XMM_Q(1)));
} }
static inline void gen_op_movq(int d_offset, int s_offset) static inline void gen_op_movq(int d_offset, int s_offset)
@ -3640,20 +3640,20 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */ case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */
case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */ case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */
gen_ldq_env_A0(s, op2_offset + gen_ldq_env_A0(s, op2_offset +
offsetof(XMMReg, XMM_Q(0))); offsetof(ZMMReg, XMM_Q(0)));
break; break;
case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */ case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */
case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */ case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */
tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0, tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0,
s->mem_index, MO_LEUL); s->mem_index, MO_LEUL);
tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, op2_offset + tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, op2_offset +
offsetof(XMMReg, XMM_L(0))); offsetof(ZMMReg, XMM_L(0)));
break; break;
case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */ case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */
tcg_gen_qemu_ld_tl(cpu_tmp0, cpu_A0, tcg_gen_qemu_ld_tl(cpu_tmp0, cpu_A0,
s->mem_index, MO_LEUW); s->mem_index, MO_LEUW);
tcg_gen_st16_tl(cpu_tmp0, cpu_env, op2_offset + tcg_gen_st16_tl(cpu_tmp0, cpu_env, op2_offset +
offsetof(XMMReg, XMM_W(0))); offsetof(ZMMReg, XMM_W(0)));
break; break;
case 0x2a: /* movntqda */ case 0x2a: /* movntqda */
gen_ldo_env_A0(s, op1_offset); gen_ldo_env_A0(s, op1_offset);