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target/arm: Convert FCSEL to decodetree

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240528203044.612851-34-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2024-05-28 13:30:44 -07:00 committed by Peter Maydell
parent 44463b96d2
commit fa31b7e168
2 changed files with 49 additions and 63 deletions
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4
target/arm/tcg/a64.decode
View File

@ -1000,6 +1000,10 @@ SQDMULH_vi 0.00 1111 10 . ..... 1100 . 0 ..... ..... @qrrx_s
SQRDMULH_vi 0.00 1111 01 .. .... 1101 . 0 ..... ..... @qrrx_h
SQRDMULH_vi 0.00 1111 10 . ..... 1101 . 0 ..... ..... @qrrx_s
# Floating-point conditional select
FCSEL 0001 1110 .. 1 rm:5 cond:4 11 rn:5 rd:5 esz=%esz_hsd
# Floating-point data-processing (3 source)
@rrrr_hsd .... .... .. . rm:5 . ra:5 rn:5 rd:5 &rrrr_e esz=%esz_hsd

108
target/arm/tcg/translate-a64.c
View File

@ -5866,6 +5866,50 @@ static bool trans_ADDP_s(DisasContext *s, arg_rr_e *a)
return true;
}
/*
* Floating-point conditional select
*/
static bool trans_FCSEL(DisasContext *s, arg_FCSEL *a)
{
TCGv_i64 t_true, t_false;
DisasCompare64 c;
switch (a->esz) {
case MO_32:
case MO_64:
break;
case MO_16:
if (!dc_isar_feature(aa64_fp16, s)) {
return false;
}
break;
default:
return false;
}
if (!fp_access_check(s)) {
return true;
}
/* Zero extend sreg & hreg inputs to 64 bits now. */
t_true = tcg_temp_new_i64();
t_false = tcg_temp_new_i64();
read_vec_element(s, t_true, a->rn, 0, a->esz);
read_vec_element(s, t_false, a->rm, 0, a->esz);
a64_test_cc(&c, a->cond);
tcg_gen_movcond_i64(c.cond, t_true, c.value, tcg_constant_i64(0),
t_true, t_false);
/*
* Note that sregs & hregs write back zeros to the high bits,
* and we've already done the zero-extension.
*/
write_fp_dreg(s, a->rd, t_true);
return true;
}
/*
* Floating-point data-processing (3 source)
*/
@ -7332,68 +7376,6 @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
}
}
/* Floating point conditional select
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
* +---+---+---+-----------+------+---+------+------+-----+------+------+
* | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
* +---+---+---+-----------+------+---+------+------+-----+------+------+
*/
static void disas_fp_csel(DisasContext *s, uint32_t insn)
{
unsigned int mos, type, rm, cond, rn, rd;
TCGv_i64 t_true, t_false;
DisasCompare64 c;
MemOp sz;
mos = extract32(insn, 29, 3);
type = extract32(insn, 22, 2);
rm = extract32(insn, 16, 5);
cond = extract32(insn, 12, 4);
rn = extract32(insn, 5, 5);
rd = extract32(insn, 0, 5);
if (mos) {
unallocated_encoding(s);
return;
}
switch (type) {
case 0:
sz = MO_32;
break;
case 1:
sz = MO_64;
break;
case 3:
sz = MO_16;
if (dc_isar_feature(aa64_fp16, s)) {
break;
}
/* fallthru */
default:
unallocated_encoding(s);
return;
}
if (!fp_access_check(s)) {
return;
}
/* Zero extend sreg & hreg inputs to 64 bits now. */
t_true = tcg_temp_new_i64();
t_false = tcg_temp_new_i64();
read_vec_element(s, t_true, rn, 0, sz);
read_vec_element(s, t_false, rm, 0, sz);
a64_test_cc(&c, cond);
tcg_gen_movcond_i64(c.cond, t_true, c.value, tcg_constant_i64(0),
t_true, t_false);
/* Note that sregs & hregs write back zeros to the high bits,
and we've already done the zero-extension. */
write_fp_dreg(s, rd, t_true);
}
/* Floating-point data-processing (1 source) - half precision */
static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
{
@ -8207,7 +8189,7 @@ static void disas_data_proc_fp(DisasContext *s, uint32_t insn)
break;
case 3:
/* Floating point conditional select */
disas_fp_csel(s, insn);
unallocated_encoding(s); /* in decodetree */
break;
case 0:
switch (ctz32(extract32(insn, 12, 4))) {