Add lxsdx
This patch adds the Load VSX Scalar Doubleowrd Indexed (lxsdx) instruction. The lower 8 bytes of the target register are undefined; this implementation leaves those bytes unaltered. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alexander Graf <agraf@suse.de>
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@ -7003,6 +7003,21 @@ static inline TCGv_i64 cpu_vsrl(int n)
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}
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}
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}
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}
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static void gen_lxsdx(DisasContext *ctx)
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{
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TCGv EA;
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if (unlikely(!ctx->vsx_enabled)) {
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gen_exception(ctx, POWERPC_EXCP_VSXU);
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return;
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}
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gen_set_access_type(ctx, ACCESS_INT);
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EA = tcg_temp_new();
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gen_addr_reg_index(ctx, EA);
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gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
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/* NOTE: cpu_vsrl is undefined */
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tcg_temp_free(EA);
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}
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static void gen_lxvd2x(DisasContext *ctx)
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static void gen_lxvd2x(DisasContext *ctx)
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{
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{
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TCGv EA;
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TCGv EA;
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@ -9502,6 +9517,7 @@ GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
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GEN_VAFORM_PAIRED(vsel, vperm, 21),
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GEN_VAFORM_PAIRED(vsel, vperm, 21),
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GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
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GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
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GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
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GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
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GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
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GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
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GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
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