hw/sh4: Coding style: White space fixes
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp> Message-Id: <91698c54fa493a4cfe93546211206439787d4b78.1635541329.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
BALATON Zoltan
Philippe Mathieu-Daudé
parent
221389657a
commit
f94bff1337
@ -75,7 +75,7 @@ typedef struct {
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qemu_irq bri;
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} sh_serial_state;
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static void sh_serial_clear_fifo(sh_serial_state * s)
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static void sh_serial_clear_fifo(sh_serial_state *s)
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{
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memset(s->rx_fifo, 0, SH_RX_FIFO_LENGTH);
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s->rx_cnt = 0;
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@ -93,7 +93,7 @@ static void sh_serial_write(void *opaque, hwaddr offs,
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printf("sh_serial: write offs=0x%02x val=0x%02x\n",
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offs, val);
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#endif
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switch(offs) {
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switch (offs) {
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case 0x00: /* SMR */
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s->smr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0x7b : 0xff);
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return;
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@ -131,7 +131,7 @@ static void sh_serial_write(void *opaque, hwaddr offs,
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#endif
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}
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if (s->feat & SH_SERIAL_FEAT_SCIF) {
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switch(offs) {
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switch (offs) {
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case 0x10: /* FSR */
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if (!(val & (1 << 6)))
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s->flags &= ~SH_SERIAL_FLAG_TEND;
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@ -178,9 +178,8 @@ static void sh_serial_write(void *opaque, hwaddr offs,
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case 0x24: /* LSR */
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return;
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}
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}
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else {
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switch(offs) {
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} else {
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switch (offs) {
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#if 0
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case 0x0c:
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ret = s->dr;
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@ -207,7 +206,7 @@ static uint64_t sh_serial_read(void *opaque, hwaddr offs,
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uint32_t ret = ~0;
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#if 0
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switch(offs) {
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switch (offs) {
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case 0x00:
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ret = s->smr;
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break;
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@ -223,7 +222,7 @@ static uint64_t sh_serial_read(void *opaque, hwaddr offs,
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}
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#endif
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if (s->feat & SH_SERIAL_FEAT_SCIF) {
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switch(offs) {
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switch (offs) {
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case 0x00: /* SMR */
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ret = s->smr;
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break;
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@ -270,9 +269,8 @@ static uint64_t sh_serial_read(void *opaque, hwaddr offs,
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ret = 0;
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break;
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}
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}
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else {
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switch(offs) {
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} else {
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switch (offs) {
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#if 0
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case 0x0c:
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ret = s->dr;
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@ -397,8 +395,7 @@ void sh_serial_init(MemoryRegion *sysmem,
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if (feat & SH_SERIAL_FEAT_SCIF) {
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s->fcr = 0;
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}
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else {
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} else {
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s->dr = 0xff;
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}
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@ -74,7 +74,7 @@ void sh_intc_toggle_source(struct intc_source *source,
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}
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}
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static void sh_intc_set_irq (void *opaque, int n, int level)
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static void sh_intc_set_irq(void *opaque, int n, int level)
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{
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struct intc_desc *desc = opaque;
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struct intc_source *source = &(desc->sources[n]);
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@ -261,10 +261,16 @@ static void sh_intc_write(void *opaque, hwaddr offset,
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&enum_ids, &first, &width, &mode);
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switch (mode) {
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case INTC_MODE_ENABLE_REG | INTC_MODE_IS_PRIO: break;
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case INTC_MODE_DUAL_SET: value |= *valuep; break;
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case INTC_MODE_DUAL_CLR: value = *valuep & ~value; break;
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default: abort();
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case INTC_MODE_ENABLE_REG | INTC_MODE_IS_PRIO:
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break;
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case INTC_MODE_DUAL_SET:
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value |= *valuep;
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break;
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case INTC_MODE_DUAL_CLR:
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value = *valuep & ~value;
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break;
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default:
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abort();
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}
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for (k = 0; k <= first; k++) {
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@ -507,7 +513,8 @@ void sh_intc_set_irl(void *opaque, int n, int level)
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int i, irl = level ^ 15;
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for (i = 0; (s = sh_intc_source(s->parent, s->next_enum_id)); i++) {
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if (i == irl)
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sh_intc_toggle_source(s, s->enable_count?0:1, s->asserted?0:1);
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sh_intc_toggle_source(s, s->enable_count ? 0 : 1,
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s->asserted ? 0 : 1);
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else
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if (s->asserted)
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sh_intc_toggle_source(s, 0, -1);
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@ -49,13 +49,12 @@ struct SHPCIState {
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uint32_t iobr;
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};
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static void sh_pci_reg_write (void *p, hwaddr addr, uint64_t val,
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unsigned size)
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static void sh_pci_reg_write(void *p, hwaddr addr, uint64_t val, unsigned size)
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{
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SHPCIState *pcic = p;
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PCIHostState *phb = PCI_HOST_BRIDGE(pcic);
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switch(addr) {
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switch (addr) {
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case 0 ... 0xfc:
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stl_le_p(pcic->dev->config + addr, val);
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break;
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@ -75,13 +74,12 @@ static void sh_pci_reg_write (void *p, hwaddr addr, uint64_t val,
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}
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}
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static uint64_t sh_pci_reg_read (void *p, hwaddr addr,
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unsigned size)
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static uint64_t sh_pci_reg_read(void *p, hwaddr addr, unsigned size)
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{
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SHPCIState *pcic = p;
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PCIHostState *phb = PCI_HOST_BRIDGE(pcic);
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switch(addr) {
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switch (addr) {
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case 0 ... 0xfc:
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return ldl_le_p(pcic->dev->config + addr);
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case 0x1c0:
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31
hw/sh4/r2d.c
31
hw/sh4/r2d.c
@ -96,19 +96,19 @@ enum r2d_fpga_irq {
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};
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static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = {
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[CF_IDE] = { 1, 1<<9 },
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[CF_CD] = { 2, 1<<8 },
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[PCI_INTA] = { 9, 1<<14 },
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[PCI_INTB] = { 10, 1<<13 },
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[PCI_INTC] = { 3, 1<<12 },
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[PCI_INTD] = { 0, 1<<11 },
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[SM501] = { 4, 1<<10 },
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[KEY] = { 5, 1<<6 },
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[RTC_A] = { 6, 1<<5 },
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[RTC_T] = { 7, 1<<4 },
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[SDCARD] = { 8, 1<<7 },
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[EXT] = { 11, 1<<0 },
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[TP] = { 12, 1<<15 },
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[CF_IDE] = { 1, 1 << 9 },
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[CF_CD] = { 2, 1 << 8 },
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[PCI_INTA] = { 9, 1 << 14 },
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[PCI_INTB] = { 10, 1 << 13 },
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[PCI_INTC] = { 3, 1 << 12 },
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[PCI_INTD] = { 0, 1 << 11 },
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[SM501] = { 4, 1 << 10 },
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[KEY] = { 5, 1 << 6 },
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[RTC_A] = { 6, 1 << 5 },
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[RTC_T] = { 7, 1 << 4 },
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[SDCARD] = { 8, 1 << 7 },
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[EXT] = { 11, 1 << 0 },
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[TP] = { 12, 1 << 15 },
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};
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static void update_irl(r2d_fpga_t *fpga)
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@ -306,7 +306,7 @@ static void r2d_init(MachineState *machine)
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/* NIC: rtl8139 on-board, and 2 slots. */
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for (i = 0; i < nb_nics; i++)
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pci_nic_init_nofail(&nd_table[i], pci_bus,
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"rtl8139", i==0 ? "2" : NULL);
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"rtl8139", i == 0 ? "2" : NULL);
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/* USB keyboard */
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usb_create_simple(usb_bus_find(-1), "usb-kbd");
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@ -330,7 +330,8 @@ static void r2d_init(MachineState *machine)
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MEMTXATTRS_UNSPECIFIED, NULL); /* cs3 SDRAM */
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address_space_stw(&address_space_memory, SH7750_BCR2, 3 << (3 * 2),
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MEMTXATTRS_UNSPECIFIED, NULL); /* cs3 32bit */
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reset_info->vector = (SDRAM_BASE + LINUX_LOAD_OFFSET) | 0xa0000000; /* Start from P2 area */
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/* Start from P2 area */
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reset_info->vector = (SDRAM_BASE + LINUX_LOAD_OFFSET) | 0xa0000000;
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}
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if (initrd_filename) {
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@ -78,7 +78,7 @@ typedef struct SH7750State {
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struct intc_desc intc;
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} SH7750State;
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static inline int has_bcr3_and_bcr4(SH7750State * s)
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static inline int has_bcr3_and_bcr4(SH7750State *s)
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{
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return s->cpu->env.features & SH_FEATURE_BCR3_AND_BCR4;
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}
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@ -87,7 +87,7 @@ static inline int has_bcr3_and_bcr4(SH7750State * s)
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* I/O ports
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*/
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int sh7750_register_io_device(SH7750State * s, sh7750_io_device * device)
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int sh7750_register_io_device(SH7750State *s, sh7750_io_device *device)
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{
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int i;
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@ -102,7 +102,7 @@ int sh7750_register_io_device(SH7750State * s, sh7750_io_device * device)
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static uint16_t portdir(uint32_t v)
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{
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#define EVENPORTMASK(n) ((v & (1<<((n)<<1))) >> (n))
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#define EVENPORTMASK(n) ((v & (1 << ((n) << 1))) >> (n))
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return
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EVENPORTMASK(15) | EVENPORTMASK(14) | EVENPORTMASK(13) |
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EVENPORTMASK(12) | EVENPORTMASK(11) | EVENPORTMASK(10) |
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@ -114,7 +114,7 @@ static uint16_t portdir(uint32_t v)
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static uint16_t portpullup(uint32_t v)
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{
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#define ODDPORTMASK(n) ((v & (1<<(((n)<<1)+1))) >> (n))
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#define ODDPORTMASK(n) ((v & (1 << (((n) << 1) + 1))) >> (n))
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return
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ODDPORTMASK(15) | ODDPORTMASK(14) | ODDPORTMASK(13) |
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ODDPORTMASK(12) | ODDPORTMASK(11) | ODDPORTMASK(10) |
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@ -123,26 +123,26 @@ static uint16_t portpullup(uint32_t v)
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ODDPORTMASK(1) | ODDPORTMASK(0);
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}
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static uint16_t porta_lines(SH7750State * s)
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static uint16_t porta_lines(SH7750State *s)
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{
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return (s->portdira & s->pdtra) | /* CPU */
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(s->periph_portdira & s->periph_pdtra) | /* Peripherals */
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(~(s->portdira | s->periph_portdira) & s->portpullupa); /* Pullups */
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}
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static uint16_t portb_lines(SH7750State * s)
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static uint16_t portb_lines(SH7750State *s)
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{
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return (s->portdirb & s->pdtrb) | /* CPU */
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(s->periph_portdirb & s->periph_pdtrb) | /* Peripherals */
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(~(s->portdirb | s->periph_portdirb) & s->portpullupb); /* Pullups */
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}
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static void gen_port_interrupts(SH7750State * s)
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static void gen_port_interrupts(SH7750State *s)
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{
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/* XXXXX interrupts not generated */
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}
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static void porta_changed(SH7750State * s, uint16_t prev)
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static void porta_changed(SH7750State *s, uint16_t prev)
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{
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uint16_t currenta, changes;
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int i, r = 0;
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@ -171,7 +171,7 @@ static void porta_changed(SH7750State * s, uint16_t prev)
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gen_port_interrupts(s);
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}
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static void portb_changed(SH7750State * s, uint16_t prev)
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static void portb_changed(SH7750State *s, uint16_t prev)
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{
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uint16_t currentb, changes;
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int i, r = 0;
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@ -228,7 +228,7 @@ static uint32_t sh7750_mem_readw(void *opaque, hwaddr addr)
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case SH7750_BCR2_A7:
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return s->bcr2;
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case SH7750_BCR3_A7:
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if(!has_bcr3_and_bcr4(s))
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if (!has_bcr3_and_bcr4(s))
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error_access("word read", addr);
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return s->bcr3;
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case SH7750_FRQCR_A7:
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@ -263,7 +263,7 @@ static uint32_t sh7750_mem_readl(void *opaque, hwaddr addr)
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case SH7750_BCR1_A7:
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return s->bcr1;
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case SH7750_BCR4_A7:
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if(!has_bcr3_and_bcr4(s))
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if (!has_bcr3_and_bcr4(s))
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error_access("long read", addr);
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return s->bcr4;
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case SH7750_WCR1_A7:
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@ -332,7 +332,7 @@ static void sh7750_mem_writew(void *opaque, hwaddr addr,
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s->bcr2 = mem_value;
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return;
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case SH7750_BCR3_A7:
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if(!has_bcr3_and_bcr4(s))
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if (!has_bcr3_and_bcr4(s))
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error_access("word write", addr);
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s->bcr3 = mem_value;
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return;
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@ -384,7 +384,7 @@ static void sh7750_mem_writel(void *opaque, hwaddr addr,
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s->bcr1 = mem_value;
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return;
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case SH7750_BCR4_A7:
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if(!has_bcr3_and_bcr4(s))
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if (!has_bcr3_and_bcr4(s))
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error_access("long write", addr);
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s->bcr4 = mem_value;
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return;
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@ -81,14 +81,15 @@ static regname_t regnames[] = {
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REGNAME(SH7750_BCR3_A7)
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REGNAME(SH7750_BCR4_A7)
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REGNAME(SH7750_SDMR2_A7)
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REGNAME(SH7750_SDMR3_A7) {(uint32_t) - 1, NULL}
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REGNAME(SH7750_SDMR3_A7)
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{ (uint32_t)-1, NULL }
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};
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const char *regname(uint32_t addr)
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{
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unsigned int i;
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for (i = 0; regnames[i].regaddr != (uint32_t) - 1; i++) {
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for (i = 0; regnames[i].regaddr != (uint32_t)-1; i++) {
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if (regnames[i].regaddr == addr)
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return regnames[i].regname;
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}
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@ -1015,7 +1015,7 @@
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*/
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/* DMA Source Address Register - SAR0, SAR1, SAR2, SAR3 */
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#define SH7750_SAR_REGOFS(n) (0xA00000 + ((n)*16)) /* offset */
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#define SH7750_SAR_REGOFS(n) (0xA00000 + ((n) * 16)) /* offset */
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#define SH7750_SAR(n) SH7750_P4_REG32(SH7750_SAR_REGOFS(n))
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#define SH7750_SAR_A7(n) SH7750_A7_REG32(SH7750_SAR_REGOFS(n))
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#define SH7750_SAR0 SH7750_SAR(0)
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@ -1028,7 +1028,7 @@
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#define SH7750_SAR3_A7 SH7750_SAR_A7(3)
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/* DMA Destination Address Register - DAR0, DAR1, DAR2, DAR3 */
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#define SH7750_DAR_REGOFS(n) (0xA00004 + ((n)*16)) /* offset */
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#define SH7750_DAR_REGOFS(n) (0xA00004 + ((n) * 16)) /* offset */
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#define SH7750_DAR(n) SH7750_P4_REG32(SH7750_DAR_REGOFS(n))
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#define SH7750_DAR_A7(n) SH7750_A7_REG32(SH7750_DAR_REGOFS(n))
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#define SH7750_DAR0 SH7750_DAR(0)
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@ -1041,7 +1041,7 @@
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#define SH7750_DAR3_A7 SH7750_DAR_A7(3)
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/* DMA Transfer Count Register - DMATCR0, DMATCR1, DMATCR2, DMATCR3 */
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#define SH7750_DMATCR_REGOFS(n) (0xA00008 + ((n)*16)) /* offset */
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#define SH7750_DMATCR_REGOFS(n) (0xA00008 + ((n) * 16)) /* offset */
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#define SH7750_DMATCR(n) SH7750_P4_REG32(SH7750_DMATCR_REGOFS(n))
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#define SH7750_DMATCR_A7(n) SH7750_A7_REG32(SH7750_DMATCR_REGOFS(n))
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#define SH7750_DMATCR0_P4 SH7750_DMATCR(0)
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@ -1054,7 +1054,7 @@
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#define SH7750_DMATCR3_A7 SH7750_DMATCR_A7(3)
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/* DMA Channel Control Register - CHCR0, CHCR1, CHCR2, CHCR3 */
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#define SH7750_CHCR_REGOFS(n) (0xA0000C + ((n)*16)) /* offset */
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#define SH7750_CHCR_REGOFS(n) (0xA0000C + ((n) * 16)) /* offset */
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#define SH7750_CHCR(n) SH7750_P4_REG32(SH7750_CHCR_REGOFS(n))
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#define SH7750_CHCR_A7(n) SH7750_A7_REG32(SH7750_CHCR_REGOFS(n))
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#define SH7750_CHCR0 SH7750_CHCR(0)
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@ -1208,9 +1208,9 @@
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#define SH7750_PCTRA_A7 SH7750_A7_REG32(SH7750_PCTRA_REGOFS)
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#define SH7750_PCTRA_PBPUP(n) 0 /* Bit n is pulled up */
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#define SH7750_PCTRA_PBNPUP(n) (1 << ((n)*2+1)) /* Bit n is not pulled up */
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||||
#define SH7750_PCTRA_PBNPUP(n) (1 << ((n) * 2 + 1)) /* Bit n is not pulled up */
|
||||
#define SH7750_PCTRA_PBINP(n) 0 /* Bit n is an input */
|
||||
#define SH7750_PCTRA_PBOUT(n) (1 << ((n)*2)) /* Bit n is an output */
|
||||
#define SH7750_PCTRA_PBOUT(n) (1 << ((n) * 2)) /* Bit n is an output */
|
||||
|
||||
/* Port Data Register A - PDTRA(half) */
|
||||
#define SH7750_PDTRA_REGOFS 0x800030 /* offset */
|
||||
@ -1225,16 +1225,16 @@
|
||||
#define SH7750_PCTRB_A7 SH7750_A7_REG32(SH7750_PCTRB_REGOFS)
|
||||
|
||||
#define SH7750_PCTRB_PBPUP(n) 0 /* Bit n is pulled up */
|
||||
#define SH7750_PCTRB_PBNPUP(n) (1 << ((n-16)*2+1)) /* Bit n is not pulled up */
|
||||
#define SH7750_PCTRB_PBNPUP(n) (1 << ((n - 16) * 2 + 1)) /* Bit n is not pulled up */
|
||||
#define SH7750_PCTRB_PBINP(n) 0 /* Bit n is an input */
|
||||
#define SH7750_PCTRB_PBOUT(n) (1 << ((n-16)*2)) /* Bit n is an output */
|
||||
#define SH7750_PCTRB_PBOUT(n) (1 << ((n - 16) * 2)) /* Bit n is an output */
|
||||
|
||||
/* Port Data Register B - PDTRB(half) */
|
||||
#define SH7750_PDTRB_REGOFS 0x800044 /* offset */
|
||||
#define SH7750_PDTRB SH7750_P4_REG32(SH7750_PDTRB_REGOFS)
|
||||
#define SH7750_PDTRB_A7 SH7750_A7_REG32(SH7750_PDTRB_REGOFS)
|
||||
|
||||
#define SH7750_PDTRB_BIT(n) (1 << ((n)-16))
|
||||
#define SH7750_PDTRB_BIT(n) (1 << ((n) - 16))
|
||||
|
||||
/* GPIO Interrupt Control Register - GPIOIC(half) */
|
||||
#define SH7750_GPIOIC_REGOFS 0x800048 /* offset */
|
||||
|
||||
@ -55,7 +55,7 @@ static void sh_timer_update(sh_timer_state *s)
|
||||
int new_level = s->int_level && (s->tcr & TIMER_TCR_UNIE);
|
||||
|
||||
if (new_level != s->old_level)
|
||||
qemu_set_irq (s->irq, new_level);
|
||||
qemu_set_irq(s->irq, new_level);
|
||||
|
||||
s->old_level = s->int_level;
|
||||
s->int_level = new_level;
|
||||
@ -113,11 +113,21 @@ static void sh_timer_write(void *opaque, hwaddr offset,
|
||||
freq = s->freq;
|
||||
/* ??? Need to recalculate expiry time after changing divisor. */
|
||||
switch (value & TIMER_TCR_TPSC) {
|
||||
case 0: freq >>= 2; break;
|
||||
case 1: freq >>= 4; break;
|
||||
case 2: freq >>= 6; break;
|
||||
case 3: freq >>= 8; break;
|
||||
case 4: freq >>= 10; break;
|
||||
case 0:
|
||||
freq >>= 2;
|
||||
break;
|
||||
case 1:
|
||||
freq >>= 4;
|
||||
break;
|
||||
case 2:
|
||||
freq >>= 6;
|
||||
break;
|
||||
case 3:
|
||||
freq >>= 8;
|
||||
break;
|
||||
case 4:
|
||||
freq >>= 10;
|
||||
break;
|
||||
case 6:
|
||||
case 7:
|
||||
if (s->feat & TIMER_FEAT_EXTCLK) {
|
||||
|
||||
@ -44,14 +44,14 @@ typedef struct {
|
||||
uint16_t portbmask_trigger;
|
||||
/* Return 0 if no action was taken */
|
||||
int (*port_change_cb) (uint16_t porta, uint16_t portb,
|
||||
uint16_t * periph_pdtra,
|
||||
uint16_t * periph_portdira,
|
||||
uint16_t * periph_pdtrb,
|
||||
uint16_t * periph_portdirb);
|
||||
uint16_t *periph_pdtra,
|
||||
uint16_t *periph_portdira,
|
||||
uint16_t *periph_pdtrb,
|
||||
uint16_t *periph_portdirb);
|
||||
} sh7750_io_device;
|
||||
|
||||
int sh7750_register_io_device(struct SH7750State *s,
|
||||
sh7750_io_device * device);
|
||||
sh7750_io_device *device);
|
||||
|
||||
/* sh_serial.c */
|
||||
#define SH_SERIAL_FEAT_SCIF (1 << 0)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user