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hw/sh4: Coding style: White space fixes

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Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Message-Id: <91698c54fa493a4cfe93546211206439787d4b78.1635541329.git.balaton@eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
BALATON Zoltan 2021-10-29 23:02:09 +02:00 committed by Philippe Mathieu-Daudé
parent 221389657a
commit f94bff1337
10 changed files with 104 additions and 90 deletions
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9
hw/char/sh_serial.c
View File

@ -178,8 +178,7 @@ static void sh_serial_write(void *opaque, hwaddr offs,
case 0x24: /* LSR */
return;
}
}
else {
} else {
switch (offs) {
#if 0
case 0x0c:
@ -270,8 +269,7 @@ static uint64_t sh_serial_read(void *opaque, hwaddr offs,
ret = 0;
break;
}
}
else {
} else {
switch (offs) {
#if 0
case 0x0c:
@ -397,8 +395,7 @@ void sh_serial_init(MemoryRegion *sysmem,
if (feat & SH_SERIAL_FEAT_SCIF) {
s->fcr = 0;
}
else {
} else {
s->dr = 0xff;
}

17
hw/intc/sh_intc.c
View File

@ -261,10 +261,16 @@ static void sh_intc_write(void *opaque, hwaddr offset,
&enum_ids, &first, &width, &mode);
switch (mode) {
case INTC_MODE_ENABLE_REG | INTC_MODE_IS_PRIO: break;
case INTC_MODE_DUAL_SET: value |= *valuep; break;
case INTC_MODE_DUAL_CLR: value = *valuep & ~value; break;
default: abort();
case INTC_MODE_ENABLE_REG | INTC_MODE_IS_PRIO:
break;
case INTC_MODE_DUAL_SET:
value |= *valuep;
break;
case INTC_MODE_DUAL_CLR:
value = *valuep & ~value;
break;
default:
abort();
}
for (k = 0; k <= first; k++) {
@ -507,7 +513,8 @@ void sh_intc_set_irl(void *opaque, int n, int level)
int i, irl = level ^ 15;
for (i = 0; (s = sh_intc_source(s->parent, s->next_enum_id)); i++) {
if (i == irl)
sh_intc_toggle_source(s, s->enable_count?0:1, s->asserted?0:1);
sh_intc_toggle_source(s, s->enable_count ? 0 : 1,
s->asserted ? 0 : 1);
else
if (s->asserted)
sh_intc_toggle_source(s, 0, -1);

6
hw/pci-host/sh_pci.c
View File

@ -49,8 +49,7 @@ struct SHPCIState {
uint32_t iobr;
};
static void sh_pci_reg_write (void *p, hwaddr addr, uint64_t val,
unsigned size)
static void sh_pci_reg_write(void *p, hwaddr addr, uint64_t val, unsigned size)
{
SHPCIState *pcic = p;
PCIHostState *phb = PCI_HOST_BRIDGE(pcic);
@ -75,8 +74,7 @@ static void sh_pci_reg_write (void *p, hwaddr addr, uint64_t val,
}
}
static uint64_t sh_pci_reg_read (void *p, hwaddr addr,
unsigned size)
static uint64_t sh_pci_reg_read(void *p, hwaddr addr, unsigned size)
{
SHPCIState *pcic = p;
PCIHostState *phb = PCI_HOST_BRIDGE(pcic);

3
hw/sh4/r2d.c
View File

@ -330,7 +330,8 @@ static void r2d_init(MachineState *machine)
MEMTXATTRS_UNSPECIFIED, NULL); /* cs3 SDRAM */
address_space_stw(&address_space_memory, SH7750_BCR2, 3 << (3 * 2),
MEMTXATTRS_UNSPECIFIED, NULL); /* cs3 32bit */
reset_info->vector = (SDRAM_BASE + LINUX_LOAD_OFFSET) | 0xa0000000; /* Start from P2 area */
/* Start from P2 area */
reset_info->vector = (SDRAM_BASE + LINUX_LOAD_OFFSET) | 0xa0000000;
}
if (initrd_filename) {

3
hw/sh4/sh7750_regnames.c
View File

@ -81,7 +81,8 @@ static regname_t regnames[] = {
REGNAME(SH7750_BCR3_A7)
REGNAME(SH7750_BCR4_A7)
REGNAME(SH7750_SDMR2_A7)
REGNAME(SH7750_SDMR3_A7) {(uint32_t) - 1, NULL}
REGNAME(SH7750_SDMR3_A7)
{ (uint32_t)-1, NULL }
};
const char *regname(uint32_t addr)

20
hw/timer/sh_timer.c
View File

@ -113,11 +113,21 @@ static void sh_timer_write(void *opaque, hwaddr offset,
freq = s->freq;
/* ??? Need to recalculate expiry time after changing divisor. */
switch (value & TIMER_TCR_TPSC) {
case 0: freq >>= 2; break;
case 1: freq >>= 4; break;
case 2: freq >>= 6; break;
case 3: freq >>= 8; break;
case 4: freq >>= 10; break;
case 0:
freq >>= 2;
break;
case 1:
freq >>= 4;
break;
case 2:
freq >>= 6;
break;
case 3:
freq >>= 8;
break;
case 4:
freq >>= 10;
break;
case 6:
case 7:
if (s->feat & TIMER_FEAT_EXTCLK) {