mirror of https://gitlab.com/qemu-project/qemu
aspeed/sli: Add AST2700 support
AST2700 SLI engine is designed to accelerate the throughput between cross-die connections. It have CPU_SLI at CPU die and IO_SLI at IO die. Introduce dummy AST2700 SLI and SLIIO models. Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Jamin Lin
Cédric Le Goater
parent
8db36a4f74
commit
f944890dfd
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@ -0,0 +1,177 @@
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/*
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* ASPEED SLI Controller
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*
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* Copyright (C) 2024 ASPEED Technology Inc.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/error-report.h"
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#include "hw/qdev-properties.h"
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#include "hw/misc/aspeed_sli.h"
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#include "qapi/error.h"
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#include "migration/vmstate.h"
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#include "trace.h"
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#define SLI_REGION_SIZE 0x500
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#define TO_REG(addr) ((addr) >> 2)
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static uint64_t aspeed_sli_read(void *opaque, hwaddr addr, unsigned int size)
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{
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AspeedSLIState *s = ASPEED_SLI(opaque);
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int reg = TO_REG(addr);
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if (reg >= ARRAY_SIZE(s->regs)) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
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__func__, addr);
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return 0;
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}
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trace_aspeed_sli_read(addr, size, s->regs[reg]);
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return s->regs[reg];
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}
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static void aspeed_sli_write(void *opaque, hwaddr addr, uint64_t data,
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unsigned int size)
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{
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AspeedSLIState *s = ASPEED_SLI(opaque);
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int reg = TO_REG(addr);
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if (reg >= ARRAY_SIZE(s->regs)) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
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__func__, addr);
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return;
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}
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trace_aspeed_sli_write(addr, size, data);
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s->regs[reg] = data;
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}
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static uint64_t aspeed_sliio_read(void *opaque, hwaddr addr, unsigned int size)
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{
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AspeedSLIState *s = ASPEED_SLI(opaque);
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int reg = TO_REG(addr);
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if (reg >= ARRAY_SIZE(s->regs)) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
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__func__, addr);
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return 0;
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}
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trace_aspeed_sliio_read(addr, size, s->regs[reg]);
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return s->regs[reg];
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}
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static void aspeed_sliio_write(void *opaque, hwaddr addr, uint64_t data,
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unsigned int size)
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{
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AspeedSLIState *s = ASPEED_SLI(opaque);
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int reg = TO_REG(addr);
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if (reg >= ARRAY_SIZE(s->regs)) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
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__func__, addr);
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return;
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}
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trace_aspeed_sliio_write(addr, size, data);
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s->regs[reg] = data;
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}
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static const MemoryRegionOps aspeed_sli_ops = {
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.read = aspeed_sli_read,
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.write = aspeed_sli_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 1,
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.max_access_size = 4,
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},
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};
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static const MemoryRegionOps aspeed_sliio_ops = {
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.read = aspeed_sliio_read,
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.write = aspeed_sliio_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 1,
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.max_access_size = 4,
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},
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};
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static void aspeed_sli_realize(DeviceState *dev, Error **errp)
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{
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AspeedSLIState *s = ASPEED_SLI(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_sli_ops, s,
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TYPE_ASPEED_SLI, SLI_REGION_SIZE);
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sysbus_init_mmio(sbd, &s->iomem);
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}
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static void aspeed_sliio_realize(DeviceState *dev, Error **errp)
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{
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AspeedSLIState *s = ASPEED_SLI(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_sliio_ops, s,
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TYPE_ASPEED_SLI, SLI_REGION_SIZE);
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sysbus_init_mmio(sbd, &s->iomem);
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}
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static void aspeed_sli_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->desc = "Aspeed SLI Controller";
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dc->realize = aspeed_sli_realize;
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}
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static const TypeInfo aspeed_sli_info = {
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.name = TYPE_ASPEED_SLI,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(AspeedSLIState),
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.class_init = aspeed_sli_class_init,
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.abstract = true,
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};
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static void aspeed_2700_sli_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->desc = "AST2700 SLI Controller";
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}
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static void aspeed_2700_sliio_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->desc = "AST2700 I/O SLI Controller";
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dc->realize = aspeed_sliio_realize;
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}
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static const TypeInfo aspeed_2700_sli_info = {
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.name = TYPE_ASPEED_2700_SLI,
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.parent = TYPE_ASPEED_SLI,
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.class_init = aspeed_2700_sli_class_init,
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};
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static const TypeInfo aspeed_2700_sliio_info = {
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.name = TYPE_ASPEED_2700_SLIIO,
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.parent = TYPE_ASPEED_SLI,
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.class_init = aspeed_2700_sliio_class_init,
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};
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static void aspeed_sli_register_types(void)
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{
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type_register_static(&aspeed_sli_info);
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type_register_static(&aspeed_2700_sli_info);
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type_register_static(&aspeed_2700_sliio_info);
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}
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type_init(aspeed_sli_register_types);
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@ -136,7 +136,8 @@ system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
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'aspeed_sbc.c',
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'aspeed_sdmc.c',
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'aspeed_xdma.c',
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'aspeed_peci.c'))
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'aspeed_peci.c',
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'aspeed_sli.c'))
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system_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-sysreg.c'))
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system_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_rng.c'))
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@ -351,3 +351,10 @@ djmemc_write(int reg, uint64_t value, unsigned int size) "reg=0x%x value=0x%"PRI
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# iosb.c
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iosb_read(int reg, uint64_t value, unsigned int size) "reg=0x%x value=0x%"PRIx64" size=%u"
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iosb_write(int reg, uint64_t value, unsigned int size) "reg=0x%x value=0x%"PRIx64" size=%u"
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# aspeed_sli.c
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aspeed_sli_write(uint64_t offset, unsigned int size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32
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aspeed_sli_read(uint64_t offset, unsigned int size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32
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aspeed_sliio_write(uint64_t offset, unsigned int size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32
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aspeed_sliio_read(uint64_t offset, unsigned int size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32
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@ -0,0 +1,27 @@
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/*
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* ASPEED SLI Controller
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*
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* Copyright (C) 2024 ASPEED Technology Inc.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef ASPEED_SLI_H
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#define ASPEED_SLI_H
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#include "hw/sysbus.h"
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#define TYPE_ASPEED_SLI "aspeed.sli"
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#define TYPE_ASPEED_2700_SLI TYPE_ASPEED_SLI "-ast2700"
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#define TYPE_ASPEED_2700_SLIIO TYPE_ASPEED_SLI "io" "-ast2700"
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OBJECT_DECLARE_SIMPLE_TYPE(AspeedSLIState, ASPEED_SLI)
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#define ASPEED_SLI_NR_REGS (0x500 >> 2)
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struct AspeedSLIState {
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SysBusDevice parent;
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MemoryRegion iomem;
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uint32_t regs[ASPEED_SLI_NR_REGS];
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};
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#endif /* ASPEED_SLI_H */
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