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hw/intc/allwinner-a10-pic: Handle IRQ levels other than 0 or 1

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In commit 2c5fa0778c we fixed an endianness bug in the Allwinner
A10 PIC model; however in the process we introduced a regression.
This is because the old code was robust against the incoming 'level'
argument being something other than 0 or 1, whereas the new code was
not.

In particular, the allwinner-sdhost code treats its IRQ line
as 0-vs-non-0 rather than 0-vs-1, so when the SD controller
set its IRQ line for any reason other than transmit the
interrupt controller would ignore it. The observed effect
was a guest timeout when rebooting the guest kernel.

Handle level values other than 0 or 1, to restore the old
behaviour.

Fixes: 2c5fa0778c ("hw/intc/allwinner-a10-pic: Don't use set_bit()/clear_bit()")
Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 20230606104609.3692557-2-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2023-06-06 11:46:08 +01:00
parent 946ccfd590
commit f837b468cd
1 changed files with 1 additions and 1 deletions
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hw/intc/allwinner-a10-pic.c
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@ -51,7 +51,7 @@ static void aw_a10_pic_set_irq(void *opaque, int irq, int level)
AwA10PICState *s = opaque; AwA10PICState *s = opaque;
uint32_t *pending_reg = &s->irq_pending[irq / 32]; uint32_t *pending_reg = &s->irq_pending[irq / 32];
*pending_reg = deposit32(*pending_reg, irq % 32, 1, level); *pending_reg = deposit32(*pending_reg, irq % 32, 1, !!level);
aw_a10_pic_update(s); aw_a10_pic_update(s);
} }