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hw/cxl: Fix missing write mask for HDM decoder target list registers

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Without being able to write these registers, no interleaving is possible.
More refined checks of HDM register state on commit to follow.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Message-Id: <20220608130804.25795-1-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Jonathan Cameron 2022-06-08 14:08:04 +01:00 committed by Michael S. Tsirkin
parent 36f18c6989
commit f824f52947
1 changed files with 11 additions and 2 deletions
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13
hw/cxl/cxl-component-utils.c
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@ -154,7 +154,8 @@ static void ras_init_common(uint32_t *reg_state, uint32_t *write_msk)
reg_state[R_CXL_RAS_ERR_CAP_CTRL] = 0x00; reg_state[R_CXL_RAS_ERR_CAP_CTRL] = 0x00;
} }
static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk) static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk,
enum reg_type type)
{ {
int decoder_count = 1; int decoder_count = 1;
int i; int i;
@ -174,6 +175,14 @@ static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk)
write_msk[R_CXL_HDM_DECODER0_SIZE_LO + i * 0x20] = 0xf0000000; write_msk[R_CXL_HDM_DECODER0_SIZE_LO + i * 0x20] = 0xf0000000;
write_msk[R_CXL_HDM_DECODER0_SIZE_HI + i * 0x20] = 0xffffffff; write_msk[R_CXL_HDM_DECODER0_SIZE_HI + i * 0x20] = 0xffffffff;
write_msk[R_CXL_HDM_DECODER0_CTRL + i * 0x20] = 0x13ff; write_msk[R_CXL_HDM_DECODER0_CTRL + i * 0x20] = 0x13ff;
if (type == CXL2_DEVICE ||
type == CXL2_TYPE3_DEVICE ||
type == CXL2_LOGICAL_DEVICE) {
write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_LO + i * 0x20] = 0xf0000000;
} else {
write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_LO + i * 0x20] = 0xffffffff;
}
write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_HI + i * 0x20] = 0xffffffff;
} }
} }
@ -239,7 +248,7 @@ void cxl_component_register_init_common(uint32_t *reg_state, uint32_t *write_msk
} }
init_cap_reg(HDM, 5, 1); init_cap_reg(HDM, 5, 1);
hdm_init_common(reg_state, write_msk); hdm_init_common(reg_state, write_msk, type);
if (caps < 5) { if (caps < 5) {
return; return;