accel/tcg: Do not issue misaligned i/o
In the single-page case we were issuing misaligned i/o to
the memory subsystem, which does not handle it properly.
Split such accesses via do_{ld,st}_mmio_*.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1800
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
190aba803f
commit
f7eaf9d702
@ -2370,16 +2370,20 @@ static uint8_t do_ld_1(CPUArchState *env, MMULookupPageData *p, int mmu_idx,
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static uint16_t do_ld_2(CPUArchState *env, MMULookupPageData *p, int mmu_idx,
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MMUAccessType type, MemOp memop, uintptr_t ra)
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{
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uint64_t ret;
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uint16_t ret;
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if (unlikely(p->flags & TLB_MMIO)) {
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return io_readx(env, p->full, mmu_idx, p->addr, ra, type, memop);
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}
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/* Perform the load host endian, then swap if necessary. */
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ret = load_atom_2(env, ra, p->haddr, memop);
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if (memop & MO_BSWAP) {
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ret = bswap16(ret);
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QEMU_IOTHREAD_LOCK_GUARD();
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ret = do_ld_mmio_beN(env, p->full, 0, p->addr, 2, mmu_idx, type, ra);
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if ((memop & MO_BSWAP) == MO_LE) {
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ret = bswap16(ret);
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}
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} else {
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/* Perform the load host endian, then swap if necessary. */
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ret = load_atom_2(env, ra, p->haddr, memop);
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if (memop & MO_BSWAP) {
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ret = bswap16(ret);
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}
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}
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return ret;
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}
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@ -2390,13 +2394,17 @@ static uint32_t do_ld_4(CPUArchState *env, MMULookupPageData *p, int mmu_idx,
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uint32_t ret;
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if (unlikely(p->flags & TLB_MMIO)) {
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return io_readx(env, p->full, mmu_idx, p->addr, ra, type, memop);
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}
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/* Perform the load host endian. */
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ret = load_atom_4(env, ra, p->haddr, memop);
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if (memop & MO_BSWAP) {
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ret = bswap32(ret);
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QEMU_IOTHREAD_LOCK_GUARD();
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ret = do_ld_mmio_beN(env, p->full, 0, p->addr, 4, mmu_idx, type, ra);
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if ((memop & MO_BSWAP) == MO_LE) {
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ret = bswap32(ret);
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}
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} else {
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/* Perform the load host endian. */
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ret = load_atom_4(env, ra, p->haddr, memop);
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if (memop & MO_BSWAP) {
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ret = bswap32(ret);
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}
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}
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return ret;
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}
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@ -2407,13 +2415,17 @@ static uint64_t do_ld_8(CPUArchState *env, MMULookupPageData *p, int mmu_idx,
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uint64_t ret;
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if (unlikely(p->flags & TLB_MMIO)) {
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return io_readx(env, p->full, mmu_idx, p->addr, ra, type, memop);
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}
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/* Perform the load host endian. */
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ret = load_atom_8(env, ra, p->haddr, memop);
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if (memop & MO_BSWAP) {
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ret = bswap64(ret);
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QEMU_IOTHREAD_LOCK_GUARD();
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ret = do_ld_mmio_beN(env, p->full, 0, p->addr, 8, mmu_idx, type, ra);
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if ((memop & MO_BSWAP) == MO_LE) {
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ret = bswap64(ret);
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}
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} else {
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/* Perform the load host endian. */
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ret = load_atom_8(env, ra, p->haddr, memop);
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if (memop & MO_BSWAP) {
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ret = bswap64(ret);
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}
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}
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return ret;
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}
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@ -2561,20 +2573,22 @@ static Int128 do_ld16_mmu(CPUArchState *env, vaddr addr,
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cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
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crosspage = mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD, &l);
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if (likely(!crosspage)) {
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/* Perform the load host endian. */
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if (unlikely(l.page[0].flags & TLB_MMIO)) {
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QEMU_IOTHREAD_LOCK_GUARD();
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a = io_readx(env, l.page[0].full, l.mmu_idx, addr,
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ra, MMU_DATA_LOAD, MO_64);
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b = io_readx(env, l.page[0].full, l.mmu_idx, addr + 8,
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ra, MMU_DATA_LOAD, MO_64);
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ret = int128_make128(HOST_BIG_ENDIAN ? b : a,
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HOST_BIG_ENDIAN ? a : b);
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a = do_ld_mmio_beN(env, l.page[0].full, 0, addr, 8,
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l.mmu_idx, MMU_DATA_LOAD, ra);
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b = do_ld_mmio_beN(env, l.page[0].full, 0, addr + 8, 8,
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l.mmu_idx, MMU_DATA_LOAD, ra);
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ret = int128_make128(b, a);
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if ((l.memop & MO_BSWAP) == MO_LE) {
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ret = bswap128(ret);
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}
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} else {
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/* Perform the load host endian. */
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ret = load_atom_16(env, ra, l.page[0].haddr, l.memop);
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}
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if (l.memop & MO_BSWAP) {
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ret = bswap128(ret);
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if (l.memop & MO_BSWAP) {
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ret = bswap128(ret);
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}
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}
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return ret;
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}
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@ -2874,7 +2888,11 @@ static void do_st_2(CPUArchState *env, MMULookupPageData *p, uint16_t val,
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int mmu_idx, MemOp memop, uintptr_t ra)
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{
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if (unlikely(p->flags & TLB_MMIO)) {
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io_writex(env, p->full, mmu_idx, val, p->addr, ra, memop);
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if ((memop & MO_BSWAP) != MO_LE) {
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val = bswap16(val);
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}
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QEMU_IOTHREAD_LOCK_GUARD();
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do_st_mmio_leN(env, p->full, val, p->addr, 2, mmu_idx, ra);
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} else if (unlikely(p->flags & TLB_DISCARD_WRITE)) {
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/* nothing */
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} else {
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@ -2890,7 +2908,11 @@ static void do_st_4(CPUArchState *env, MMULookupPageData *p, uint32_t val,
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int mmu_idx, MemOp memop, uintptr_t ra)
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{
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if (unlikely(p->flags & TLB_MMIO)) {
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io_writex(env, p->full, mmu_idx, val, p->addr, ra, memop);
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if ((memop & MO_BSWAP) != MO_LE) {
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val = bswap32(val);
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}
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QEMU_IOTHREAD_LOCK_GUARD();
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do_st_mmio_leN(env, p->full, val, p->addr, 4, mmu_idx, ra);
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} else if (unlikely(p->flags & TLB_DISCARD_WRITE)) {
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/* nothing */
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} else {
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@ -2906,7 +2928,11 @@ static void do_st_8(CPUArchState *env, MMULookupPageData *p, uint64_t val,
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int mmu_idx, MemOp memop, uintptr_t ra)
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{
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if (unlikely(p->flags & TLB_MMIO)) {
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io_writex(env, p->full, mmu_idx, val, p->addr, ra, memop);
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if ((memop & MO_BSWAP) != MO_LE) {
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val = bswap64(val);
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}
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QEMU_IOTHREAD_LOCK_GUARD();
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do_st_mmio_leN(env, p->full, val, p->addr, 8, mmu_idx, ra);
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} else if (unlikely(p->flags & TLB_DISCARD_WRITE)) {
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/* nothing */
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} else {
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@ -3029,22 +3055,22 @@ static void do_st16_mmu(CPUArchState *env, vaddr addr, Int128 val,
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cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
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crosspage = mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE, &l);
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if (likely(!crosspage)) {
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/* Swap to host endian if necessary, then store. */
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if (l.memop & MO_BSWAP) {
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val = bswap128(val);
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}
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if (unlikely(l.page[0].flags & TLB_MMIO)) {
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QEMU_IOTHREAD_LOCK_GUARD();
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if (HOST_BIG_ENDIAN) {
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b = int128_getlo(val), a = int128_gethi(val);
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} else {
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a = int128_getlo(val), b = int128_gethi(val);
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if ((l.memop & MO_BSWAP) != MO_LE) {
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val = bswap128(val);
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}
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io_writex(env, l.page[0].full, l.mmu_idx, a, addr, ra, MO_64);
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io_writex(env, l.page[0].full, l.mmu_idx, b, addr + 8, ra, MO_64);
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a = int128_getlo(val);
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b = int128_gethi(val);
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QEMU_IOTHREAD_LOCK_GUARD();
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do_st_mmio_leN(env, l.page[0].full, a, addr, 8, l.mmu_idx, ra);
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do_st_mmio_leN(env, l.page[0].full, b, addr + 8, 8, l.mmu_idx, ra);
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} else if (unlikely(l.page[0].flags & TLB_DISCARD_WRITE)) {
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/* nothing */
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} else {
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/* Swap to host endian if necessary, then store. */
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if (l.memop & MO_BSWAP) {
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val = bswap128(val);
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}
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store_atom_16(env, ra, l.page[0].haddr, l.memop, val);
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}
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return;
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