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This fixes two bugs in the RISC-V port. One is a bug in the

Browse Source 
Ibex PLIC, the other fixes the Hypvervisor access functions.
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Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20201109' into staging

This fixes two bugs in the RISC-V port. One is a bug in the
Ibex PLIC, the other fixes the Hypvervisor access functions.

# gpg: Signature made Tue 10 Nov 2020 03:53:49 GMT
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-to-apply-20201109:
  hw/intc/ibex_plic: Clear the claim register when read
  target/riscv: Split the Hypervisor execute load helpers
  target/riscv: Remove the hyp load and store functions
  target/riscv: Remove the HS_TWO_STAGE flag
  target/riscv: Set the virtualised MMU mode when doing hyp accesses
  target/riscv: Add a virtualised MMU Mode

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2020-11-10 09:24:56 +00:00
commit f7e1914ada
9 changed files with 115 additions and 255 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
hw/intc/ibex_plic.c
View File

@ -139,6 +139,9 @@ static uint64_t ibex_plic_read(void *opaque, hwaddr addr,
/* Return the current claimed interrupt */
ret = s->claim;
/* Clear the claimed interrupt */
s->claim = 0x00000000;
/* Update the interrupt status after the claim */
ibex_plic_update(s);
}

11
target/riscv/cpu-param.h
View File

@ -18,6 +18,15 @@
# define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */
#endif
#define TARGET_PAGE_BITS 12 /* 4 KiB Pages */
#define NB_MMU_MODES 4
/*
* The current MMU Modes are:
* - U mode 0b000
* - S mode 0b001
* - M mode 0b011
* - U mode HLV/HLVX/HSV 0b100
* - S mode HLV/HLVX/HSV 0b101
* - M mode HLV/HLVX/HSV 0b111
*/
#define NB_MMU_MODES 8
#endif

19
target/riscv/cpu.h
View File

@ -323,8 +323,7 @@ bool riscv_cpu_virt_enabled(CPURISCVState *env);
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env);
void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable);
bool riscv_cpu_two_stage_lookup(CPURISCVState *env);
void riscv_cpu_set_two_stage_lookup(CPURISCVState *env, bool enable);
bool riscv_cpu_two_stage_lookup(int mmu_idx);
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
@ -363,7 +362,9 @@ void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
#define TB_FLAGS_MMU_MASK 3
#define TB_FLAGS_MMU_MASK 7
#define TB_FLAGS_PRIV_MMU_MASK 3
#define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2)
#define TB_FLAGS_MSTATUS_FS MSTATUS_FS
typedef CPURISCVState CPUArchState;
@ -374,6 +375,8 @@ FIELD(TB_FLAGS, VL_EQ_VLMAX, 2, 1)
FIELD(TB_FLAGS, LMUL, 3, 2)
FIELD(TB_FLAGS, SEW, 5, 3)
FIELD(TB_FLAGS, VILL, 8, 1)
/* Is a Hypervisor instruction load/store allowed? */
FIELD(TB_FLAGS, HLSX, 9, 1)
/*
* A simplification for VLMAX
@ -420,7 +423,17 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
if (riscv_cpu_fp_enabled(env)) {
flags |= env->mstatus & MSTATUS_FS;
}
if (riscv_has_ext(env, RVH)) {
if (env->priv == PRV_M ||
(env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
(env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
get_field(env->hstatus, HSTATUS_HU))) {
flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
}
}
#endif
*pflags = flags;
}

1
target/riscv/cpu_bits.h
View File

@ -469,7 +469,6 @@
* page table fault.
*/
#define FORCE_HS_EXCEP 2
#define HS_TWO_STAGE 4
/* RV32 satp CSR field masks */
#define SATP32_MODE 0x80000000

62
target/riscv/cpu_helper.c
View File

@ -207,22 +207,9 @@ void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable)
env->virt = set_field(env->virt, FORCE_HS_EXCEP, enable);
}
bool riscv_cpu_two_stage_lookup(CPURISCVState *env)
bool riscv_cpu_two_stage_lookup(int mmu_idx)
{
if (!riscv_has_ext(env, RVH)) {
return false;
}
return get_field(env->virt, HS_TWO_STAGE);
}
void riscv_cpu_set_two_stage_lookup(CPURISCVState *env, bool enable)
{
if (!riscv_has_ext(env, RVH)) {
return;
}
env->virt = set_field(env->virt, HS_TWO_STAGE, enable);
return mmu_idx & TB_FLAGS_PRIV_HYP_ACCESS_MASK;
}
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
@ -323,7 +310,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
* (riscv_cpu_do_interrupt) is correct */
MemTxResult res;
MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
int mode = mmu_idx;
int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK;
bool use_background = false;
/*
@ -333,7 +320,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
* was called. Background registers will be used if the guest has
* forced a two stage translation to be on (in HS or M mode).
*/
if (riscv_cpu_two_stage_lookup(env) && access_type != MMU_INST_FETCH) {
if (!riscv_cpu_virt_enabled(env) && riscv_cpu_two_stage_lookup(mmu_idx)) {
use_background = true;
}
@ -572,7 +559,7 @@ restart:
static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
MMUAccessType access_type, bool pmp_violation,
bool first_stage)
bool first_stage, bool two_stage)
{
CPUState *cs = env_cpu(env);
int page_fault_exceptions;
@ -595,8 +582,7 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
}
break;
case MMU_DATA_LOAD:
if ((riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(env)) &&
!first_stage) {
if (two_stage && !first_stage) {
cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
} else {
cs->exception_index = page_fault_exceptions ?
@ -604,8 +590,7 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
}
break;
case MMU_DATA_STORE:
if ((riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(env)) &&
!first_stage) {
if (two_stage && !first_stage) {
cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
} else {
cs->exception_index = page_fault_exceptions ?
@ -696,6 +681,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
int prot, prot2;
bool pmp_violation = false;
bool first_stage_error = true;
bool two_stage_lookup = false;
int ret = TRANSLATE_FAIL;
int mode = mmu_idx;
target_ulong tlb_size = 0;
@ -715,11 +701,12 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
access_type != MMU_INST_FETCH &&
get_field(env->mstatus, MSTATUS_MPRV) &&
get_field(env->mstatus, MSTATUS_MPV)) {
riscv_cpu_set_two_stage_lookup(env, true);
two_stage_lookup = true;
}
if (riscv_cpu_virt_enabled(env) ||
(riscv_cpu_two_stage_lookup(env) && access_type != MMU_INST_FETCH)) {
((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
access_type != MMU_INST_FETCH)) {
/* Two stage lookup */
ret = get_physical_address(env, &pa, &prot, address,
&env->guest_phys_fault_addr, access_type,
@ -782,14 +769,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
__func__, address, ret, pa, prot);
}
/* We did the two stage lookup based on MPRV, unset the lookup */
if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
access_type != MMU_INST_FETCH &&
get_field(env->mstatus, MSTATUS_MPRV) &&
get_field(env->mstatus, MSTATUS_MPV)) {
riscv_cpu_set_two_stage_lookup(env, false);
}
if (riscv_feature(env, RISCV_FEATURE_PMP) &&
(ret == TRANSLATE_SUCCESS) &&
!pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
@ -811,7 +790,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
} else if (probe) {
return false;
} else {
raise_mmu_exception(env, address, access_type, pmp_violation, first_stage_error);
raise_mmu_exception(env, address, access_type, pmp_violation,
first_stage_error,
riscv_cpu_virt_enabled(env) ||
riscv_cpu_two_stage_lookup(mmu_idx));
riscv_raise_exception(env, cs->exception_index, retaddr);
}
@ -915,9 +897,16 @@ void riscv_cpu_do_interrupt(CPUState *cs)
/* handle the trap in S-mode */
if (riscv_has_ext(env, RVH)) {
target_ulong hdeleg = async ? env->hideleg : env->hedeleg;
bool two_stage_lookup = false;
if ((riscv_cpu_virt_enabled(env) ||
riscv_cpu_two_stage_lookup(env)) && write_tval) {
if (env->priv == PRV_M ||
(env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
(env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
get_field(env->hstatus, HSTATUS_HU))) {
two_stage_lookup = true;
}
if ((riscv_cpu_virt_enabled(env) || two_stage_lookup) && write_tval) {
/*
* If we are writing a guest virtual address to stval, set
* this to 1. If we are trapping to VS we will set this to 0
@ -955,11 +944,10 @@ void riscv_cpu_do_interrupt(CPUState *cs)
riscv_cpu_set_force_hs_excep(env, 0);
} else {
/* Trap into HS mode */
if (!riscv_cpu_two_stage_lookup(env)) {
if (!two_stage_lookup) {
env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
riscv_cpu_virt_enabled(env));
}
riscv_cpu_set_two_stage_lookup(env, false);
htval = env->guest_phys_fault_addr;
}
}

5
target/riscv/helper.h
View File

@ -81,9 +81,8 @@ DEF_HELPER_1(tlb_flush, void, env)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_1(hyp_tlb_flush, void, env)
DEF_HELPER_1(hyp_gvma_tlb_flush, void, env)
DEF_HELPER_4(hyp_load, tl, env, tl, tl, tl)
DEF_HELPER_5(hyp_store, void, env, tl, tl, tl, tl)
DEF_HELPER_4(hyp_x_load, tl, env, tl, tl, tl)
DEF_HELPER_2(hyp_hlvx_hu, tl, env, tl)
DEF_HELPER_2(hyp_hlvx_wu, tl, env, tl)
#endif
/* Vector functions */

143
target/riscv/insn_trans/trans_rvh.c.inc
View File

@ -16,26 +16,34 @@
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef CONFIG_USER_ONLY
static void check_access(DisasContext *ctx) {
if (!ctx->hlsx) {
if (ctx->virt_enabled) {
generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT);
} else {
generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
}
}
}
#endif
static bool trans_hlv_b(DisasContext *ctx, arg_hlv_b *a)
{
REQUIRE_EXT(ctx, RVH);
#ifndef CONFIG_USER_ONLY
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
TCGv mem_idx = tcg_temp_new();
TCGv memop = tcg_temp_new();
check_access(ctx);
gen_get_gpr(t0, a->rs1);
tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
tcg_gen_movi_tl(memop, MO_SB);
gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_SB);
gen_set_gpr(a->rd, t1);
tcg_temp_free(t0);
tcg_temp_free(t1);
tcg_temp_free(mem_idx);
tcg_temp_free(memop);
return true;
#else
return false;
@ -48,20 +56,16 @@ static bool trans_hlv_h(DisasContext *ctx, arg_hlv_h *a)
#ifndef CONFIG_USER_ONLY
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
TCGv mem_idx = tcg_temp_new();
TCGv memop = tcg_temp_new();
check_access(ctx);
gen_get_gpr(t0, a->rs1);
tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
tcg_gen_movi_tl(memop, MO_TESW);
gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TESW);
gen_set_gpr(a->rd, t1);
tcg_temp_free(t0);
tcg_temp_free(t1);
tcg_temp_free(mem_idx);
tcg_temp_free(memop);
return true;
#else
return false;
@ -74,20 +78,16 @@ static bool trans_hlv_w(DisasContext *ctx, arg_hlv_w *a)
#ifndef CONFIG_USER_ONLY
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
TCGv mem_idx = tcg_temp_new();
TCGv memop = tcg_temp_new();
check_access(ctx);
gen_get_gpr(t0, a->rs1);
tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
tcg_gen_movi_tl(memop, MO_TESL);
gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TESL);
gen_set_gpr(a->rd, t1);
tcg_temp_free(t0);
tcg_temp_free(t1);
tcg_temp_free(mem_idx);
tcg_temp_free(memop);
return true;
#else
return false;
@ -100,20 +100,16 @@ static bool trans_hlv_bu(DisasContext *ctx, arg_hlv_bu *a)
#ifndef CONFIG_USER_ONLY
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
TCGv mem_idx = tcg_temp_new();
TCGv memop = tcg_temp_new();
check_access(ctx);
gen_get_gpr(t0, a->rs1);
tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
tcg_gen_movi_tl(memop, MO_UB);
gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_UB);
gen_set_gpr(a->rd, t1);
tcg_temp_free(t0);
tcg_temp_free(t1);
tcg_temp_free(mem_idx);
tcg_temp_free(memop);
return true;
#else
return false;
@ -126,20 +122,15 @@ static bool trans_hlv_hu(DisasContext *ctx, arg_hlv_hu *a)
#ifndef CONFIG_USER_ONLY
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
TCGv mem_idx = tcg_temp_new();
TCGv memop = tcg_temp_new();
check_access(ctx);
gen_get_gpr(t0, a->rs1);
tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
tcg_gen_movi_tl(memop, MO_TEUW);
gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TEUW);
gen_set_gpr(a->rd, t1);
tcg_temp_free(t0);
tcg_temp_free(t1);
tcg_temp_free(mem_idx);
tcg_temp_free(memop);
return true;
#else
return false;
@ -152,20 +143,16 @@ static bool trans_hsv_b(DisasContext *ctx, arg_hsv_b *a)
#ifndef CONFIG_USER_ONLY
TCGv t0 = tcg_temp_new();
TCGv dat = tcg_temp_new();
TCGv mem_idx = tcg_temp_new();
TCGv memop = tcg_temp_new();
check_access(ctx);
gen_get_gpr(t0, a->rs1);
gen_get_gpr(dat, a->rs2);
tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
tcg_gen_movi_tl(memop, MO_SB);
gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop);
tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_SB);
tcg_temp_free(t0);
tcg_temp_free(dat);
tcg_temp_free(mem_idx);
tcg_temp_free(memop);
return true;
#else
return false;
@ -178,20 +165,16 @@ static bool trans_hsv_h(DisasContext *ctx, arg_hsv_h *a)
#ifndef CONFIG_USER_ONLY
TCGv t0 = tcg_temp_new();
TCGv dat = tcg_temp_new();
TCGv mem_idx = tcg_temp_new();
TCGv memop = tcg_temp_new();
check_access(ctx);
gen_get_gpr(t0, a->rs1);
gen_get_gpr(dat, a->rs2);
tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
tcg_gen_movi_tl(memop, MO_TESW);
gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop);
tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TESW);
tcg_temp_free(t0);
tcg_temp_free(dat);
tcg_temp_free(mem_idx);
tcg_temp_free(memop);
return true;
#else
return false;
@ -204,20 +187,16 @@ static bool trans_hsv_w(DisasContext *ctx, arg_hsv_w *a)
#ifndef CONFIG_USER_ONLY
TCGv t0 = tcg_temp_new();
TCGv dat = tcg_temp_new();
TCGv mem_idx = tcg_temp_new();
TCGv memop = tcg_temp_new();
check_access(ctx);
gen_get_gpr(t0, a->rs1);
gen_get_gpr(dat, a->rs2);
tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
tcg_gen_movi_tl(memop, MO_TESL);
gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop);
tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TESL);
tcg_temp_free(t0);
tcg_temp_free(dat);
tcg_temp_free(mem_idx);
tcg_temp_free(memop);
return true;
#else
return false;
@ -231,20 +210,16 @@ static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_wu *a)
#ifndef CONFIG_USER_ONLY
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
TCGv mem_idx = tcg_temp_new();
TCGv memop = tcg_temp_new();
check_access(ctx);
gen_get_gpr(t0, a->rs1);
tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
tcg_gen_movi_tl(memop, MO_TEUL);
gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TEUL);
gen_set_gpr(a->rd, t1);
tcg_temp_free(t0);
tcg_temp_free(t1);
tcg_temp_free(mem_idx);
tcg_temp_free(memop);
return true;
#else
return false;
@ -257,20 +232,16 @@ static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d *a)
#ifndef CONFIG_USER_ONLY
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
TCGv mem_idx = tcg_temp_new();
TCGv memop = tcg_temp_new();
check_access(ctx);
gen_get_gpr(t0, a->rs1);
tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
tcg_gen_movi_tl(memop, MO_TEQ);
gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TEQ);
gen_set_gpr(a->rd, t1);
tcg_temp_free(t0);
tcg_temp_free(t1);
tcg_temp_free(mem_idx);
tcg_temp_free(memop);
return true;
#else
return false;
@ -283,20 +254,16 @@ static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a)
#ifndef CONFIG_USER_ONLY
TCGv t0 = tcg_temp_new();
TCGv dat = tcg_temp_new();
TCGv mem_idx = tcg_temp_new();
TCGv memop = tcg_temp_new();
check_access(ctx);
gen_get_gpr(t0, a->rs1);
gen_get_gpr(dat, a->rs2);
tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
tcg_gen_movi_tl(memop, MO_TEQ);
gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop);
tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TEQ);
tcg_temp_free(t0);
tcg_temp_free(dat);
tcg_temp_free(mem_idx);
tcg_temp_free(memop);
return true;
#else
return false;
@ -310,20 +277,16 @@ static bool trans_hlvx_hu(DisasContext *ctx, arg_hlvx_hu *a)
#ifndef CONFIG_USER_ONLY
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
TCGv mem_idx = tcg_temp_new();
TCGv memop = tcg_temp_new();
check_access(ctx);
gen_get_gpr(t0, a->rs1);
tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
tcg_gen_movi_tl(memop, MO_TEUW);
gen_helper_hyp_x_load(t1, cpu_env, t0, mem_idx, memop);
gen_helper_hyp_hlvx_hu(t1, cpu_env, t0);
gen_set_gpr(a->rd, t1);
tcg_temp_free(t0);
tcg_temp_free(t1);
tcg_temp_free(mem_idx);
tcg_temp_free(memop);
return true;
#else
return false;
@ -336,20 +299,16 @@ static bool trans_hlvx_wu(DisasContext *ctx, arg_hlvx_wu *a)
#ifndef CONFIG_USER_ONLY
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
TCGv mem_idx = tcg_temp_new();
TCGv memop = tcg_temp_new();
check_access(ctx);
gen_get_gpr(t0, a->rs1);
tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
tcg_gen_movi_tl(memop, MO_TEUL);
gen_helper_hyp_x_load(t1, cpu_env, t0, mem_idx, memop);
gen_helper_hyp_hlvx_wu(t1, cpu_env, t0);
gen_set_gpr(a->rd, t1);
tcg_temp_free(t0);
tcg_temp_free(t1);
tcg_temp_free(mem_idx);
tcg_temp_free(memop);
return true;
#else
return false;

124
target/riscv/op_helper.c
View File

@ -227,130 +227,18 @@ void helper_hyp_gvma_tlb_flush(CPURISCVState *env)
helper_hyp_tlb_flush(env);
}
target_ulong helper_hyp_load(CPURISCVState *env, target_ulong address,
target_ulong attrs, target_ulong memop)
target_ulong helper_hyp_hlvx_hu(CPURISCVState *env, target_ulong address)
{
if (env->priv == PRV_M ||
(env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
(env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
get_field(env->hstatus, HSTATUS_HU))) {
target_ulong pte;
int mmu_idx = cpu_mmu_index(env, true) | TB_FLAGS_PRIV_HYP_ACCESS_MASK;
riscv_cpu_set_two_stage_lookup(env, true);
switch (memop) {
case MO_SB:
pte = cpu_ldsb_data_ra(env, address, GETPC());
break;
case MO_UB:
pte = cpu_ldub_data_ra(env, address, GETPC());
break;
case MO_TESW:
pte = cpu_ldsw_data_ra(env, address, GETPC());
break;
case MO_TEUW:
pte = cpu_lduw_data_ra(env, address, GETPC());
break;
case MO_TESL:
pte = cpu_ldl_data_ra(env, address, GETPC());
break;
case MO_TEUL:
pte = cpu_ldl_data_ra(env, address, GETPC());
break;
case MO_TEQ:
pte = cpu_ldq_data_ra(env, address, GETPC());
break;
default:
g_assert_not_reached();
}
riscv_cpu_set_two_stage_lookup(env, false);
return pte;
}
if (riscv_cpu_virt_enabled(env)) {
riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
} else {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
return 0;
return cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC());
}
void helper_hyp_store(CPURISCVState *env, target_ulong address,
target_ulong val, target_ulong attrs, target_ulong memop)
target_ulong helper_hyp_hlvx_wu(CPURISCVState *env, target_ulong address)
{
if (env->priv == PRV_M ||
(env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
(env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
get_field(env->hstatus, HSTATUS_HU))) {
riscv_cpu_set_two_stage_lookup(env, true);
int mmu_idx = cpu_mmu_index(env, true) | TB_FLAGS_PRIV_HYP_ACCESS_MASK;
switch (memop) {
case MO_SB:
case MO_UB:
cpu_stb_data_ra(env, address, val, GETPC());
break;
case MO_TESW:
case MO_TEUW:
cpu_stw_data_ra(env, address, val, GETPC());
break;
case MO_TESL:
case MO_TEUL:
cpu_stl_data_ra(env, address, val, GETPC());
break;
case MO_TEQ:
cpu_stq_data_ra(env, address, val, GETPC());
break;
default:
g_assert_not_reached();
}
riscv_cpu_set_two_stage_lookup(env, false);
return;
}
if (riscv_cpu_virt_enabled(env)) {
riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
} else {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
}
target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address,
target_ulong attrs, target_ulong memop)
{
if (env->priv == PRV_M ||
(env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
(env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
get_field(env->hstatus, HSTATUS_HU))) {
target_ulong pte;
riscv_cpu_set_two_stage_lookup(env, true);
switch (memop) {
case MO_TEUW:
pte = cpu_lduw_data_ra(env, address, GETPC());
break;
case MO_TEUL:
pte = cpu_ldl_data_ra(env, address, GETPC());
break;
default:
g_assert_not_reached();
}
riscv_cpu_set_two_stage_lookup(env, false);
return pte;
}
if (riscv_cpu_virt_enabled(env)) {
riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
} else {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
return 0;
return cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC());
}
#endif /* !CONFIG_USER_ONLY */

2
target/riscv/translate.c
View File

@ -56,6 +56,7 @@ typedef struct DisasContext {
to reset this known value. */
int frm;
bool ext_ifencei;
bool hlsx;
/* vector extension */
bool vill;
uint8_t lmul;
@ -807,6 +808,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->frm = -1; /* unknown rounding mode */
ctx->ext_ifencei = cpu->cfg.ext_ifencei;
ctx->vlen = cpu->cfg.vlen;
ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX);
ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL);
ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);
ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL);