target/arm: Implement aarch64 SUDOT, USDOT
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210525010358.152808-84-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -4216,6 +4216,11 @@ static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id)
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return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2;
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}
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static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0;
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}
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static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
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@ -12175,6 +12175,13 @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
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}
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feature = dc_isar_feature(aa64_dp, s);
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break;
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case 0x03: /* USDOT */
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if (size != MO_32) {
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unallocated_encoding(s);
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return;
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}
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feature = dc_isar_feature(aa64_i8mm, s);
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break;
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case 0x18: /* FCMLA, #0 */
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case 0x19: /* FCMLA, #90 */
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case 0x1a: /* FCMLA, #180 */
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@ -12215,6 +12222,10 @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
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u ? gen_helper_gvec_udot_b : gen_helper_gvec_sdot_b);
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return;
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case 0x3: /* USDOT */
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gen_gvec_op4_ool(s, is_q, rd, rn, rm, rd, 0, gen_helper_gvec_usdot_b);
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return;
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case 0x8: /* FCMLA, #0 */
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case 0x9: /* FCMLA, #90 */
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case 0xa: /* FCMLA, #180 */
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@ -13360,6 +13371,13 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
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return;
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}
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break;
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case 0x0f: /* SUDOT, USDOT */
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if (is_scalar || (size & 1) || !dc_isar_feature(aa64_i8mm, s)) {
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unallocated_encoding(s);
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return;
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}
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size = MO_32;
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break;
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case 0x11: /* FCMLA #0 */
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case 0x13: /* FCMLA #90 */
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case 0x15: /* FCMLA #180 */
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@ -13474,6 +13492,13 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
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u ? gen_helper_gvec_udot_idx_b
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: gen_helper_gvec_sdot_idx_b);
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return;
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case 0x0f: /* SUDOT, USDOT */
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gen_gvec_op4_ool(s, is_q, rd, rn, rm, rd, index,
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extract32(insn, 23, 1)
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? gen_helper_gvec_usdot_idx_b
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: gen_helper_gvec_sudot_idx_b);
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return;
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case 0x11: /* FCMLA #0 */
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case 0x13: /* FCMLA #90 */
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case 0x15: /* FCMLA #180 */
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