tests/plugin: add instruction execution breakdown
This gives a break down of instruction classes and individual instruction types. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Alex Bennée
parent
a208ba09bd
commit
f79e8fa3b7
@ -11,6 +11,7 @@ NAMES += empty
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NAMES += insn
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NAMES += mem
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NAMES += hotblocks
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NAMES += howvec
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SONAMES := $(addsuffix .so,$(addprefix lib,$(NAMES)))
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352
tests/plugin/howvec.c
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352
tests/plugin/howvec.c
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@ -0,0 +1,352 @@
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/*
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* Copyright (C) 2019, Alex Bennée <alex.bennee@linaro.org>
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*
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* How vectorised is this code?
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*
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* Attempt to measure the amount of vectorisation that has been done
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* on some code by counting classes of instruction.
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*
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* License: GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include <inttypes.h>
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#include <assert.h>
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#include <stdlib.h>
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#include <inttypes.h>
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#include <string.h>
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#include <unistd.h>
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#include <stdio.h>
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#include <glib.h>
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#include <qemu-plugin.h>
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#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
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typedef enum {
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COUNT_CLASS,
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COUNT_INDIVIDUAL,
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COUNT_NONE
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} CountType;
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static int limit = 50;
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static bool do_inline;
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static bool verbose;
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static GMutex lock;
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static GHashTable *insns;
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typedef struct {
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const char *class;
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const char *opt;
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uint32_t mask;
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uint32_t pattern;
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CountType what;
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uint64_t count;
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} InsnClassExecCount;
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typedef struct {
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char *insn;
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uint32_t opcode;
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uint64_t count;
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InsnClassExecCount *class;
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} InsnExecCount;
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/*
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* Matchers for classes of instructions, order is important.
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*
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* Your most precise match must be before looser matches. If no match
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* is found in the table we can create an individual entry.
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*
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* 31..28 27..24 23..20 19..16 15..12 11..8 7..4 3..0
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*/
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static InsnClassExecCount aarch64_insn_classes[] = {
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/* "Reserved"" */
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{ " UDEF", "udef", 0xffff0000, 0x00000000, COUNT_NONE},
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{ " SVE", "sve", 0x1e000000, 0x04000000, COUNT_CLASS},
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{ "Reserved", "res", 0x1e000000, 0x00000000, COUNT_CLASS},
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/* Data Processing Immediate */
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{ " PCrel addr", "pcrel", 0x1f000000, 0x10000000, COUNT_CLASS},
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{ " Add/Sub (imm,tags)","asit", 0x1f800000, 0x11800000, COUNT_CLASS},
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{ " Add/Sub (imm)", "asi", 0x1f000000, 0x11000000, COUNT_CLASS},
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{ " Logical (imm)", "logi", 0x1f800000, 0x12000000, COUNT_CLASS},
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{ " Move Wide (imm)", "movwi", 0x1f800000, 0x12800000, COUNT_CLASS},
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{ " Bitfield", "bitf", 0x1f800000, 0x13000000, COUNT_CLASS},
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{ " Extract", "extr", 0x1f800000, 0x13800000, COUNT_CLASS},
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{ "Data Proc Imm", "dpri", 0x1c000000, 0x10000000, COUNT_CLASS},
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/* Branches */
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{ " Cond Branch (imm)", "cndb", 0xfe000000, 0x54000000, COUNT_CLASS},
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{ " Exception Gen", "excp", 0xff000000, 0xd4000000, COUNT_CLASS},
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{ " NOP", "nop", 0xffffffff, 0xd503201f, COUNT_NONE},
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{ " Hints", "hint", 0xfffff000, 0xd5032000, COUNT_CLASS},
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{ " Barriers", "barr", 0xfffff000, 0xd5033000, COUNT_CLASS},
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{ " PSTATE", "psta", 0xfff8f000, 0xd5004000, COUNT_CLASS},
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{ " System Insn", "sins", 0xffd80000, 0xd5080000, COUNT_CLASS},
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{ " System Reg", "sreg", 0xffd00000, 0xd5100000, COUNT_CLASS},
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{ " Branch (reg)", "breg", 0xfe000000, 0xd6000000, COUNT_CLASS},
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{ " Branch (imm)", "bimm", 0x7c000000, 0x14000000, COUNT_CLASS},
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{ " Cmp & Branch", "cmpb", 0x7e000000, 0x34000000, COUNT_CLASS},
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{ " Tst & Branch", "tstb", 0x7e000000, 0x36000000, COUNT_CLASS},
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{ "Branches", "branch", 0x1c000000, 0x14000000, COUNT_CLASS},
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/* Loads and Stores */
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{ " AdvSimd ldstmult", "advlsm", 0xbfbf0000, 0x0c000000, COUNT_CLASS},
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{ " AdvSimd ldstmult++","advlsmp",0xbfb00000, 0x0c800000, COUNT_CLASS},
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{ " AdvSimd ldst", "advlss", 0xbf9f0000, 0x0d000000, COUNT_CLASS},
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{ " AdvSimd ldst++", "advlssp",0xbf800000, 0x0d800000, COUNT_CLASS},
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{ " ldst excl", "ldstx", 0x3f000000, 0x08000000, COUNT_CLASS},
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{ " Prefetch", "prfm", 0xff000000, 0xd8000000, COUNT_CLASS},
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{ " Load Reg (lit)", "ldlit", 0x1b000000, 0x18000000, COUNT_CLASS},
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{ " ldst noalloc pair", "ldstnap",0x3b800000, 0x28000000, COUNT_CLASS},
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{ " ldst pair", "ldstp", 0x38000000, 0x28000000, COUNT_CLASS},
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{ " ldst reg", "ldstr", 0x3b200000, 0x38000000, COUNT_CLASS},
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{ " Atomic ldst", "atomic", 0x3b200c00, 0x38200000, COUNT_CLASS},
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{ " ldst reg (reg off)","ldstro", 0x3b200b00, 0x38200800, COUNT_CLASS},
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{ " ldst reg (pac)", "ldstpa", 0x3b200200, 0x38200800, COUNT_CLASS},
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{ " ldst reg (imm)", "ldsti", 0x3b000000, 0x39000000, COUNT_CLASS},
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{ "Loads & Stores", "ldst", 0x0a000000, 0x08000000, COUNT_CLASS},
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/* Data Processing Register */
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{ "Data Proc Reg", "dprr", 0x0e000000, 0x0a000000, COUNT_CLASS},
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/* Scalar FP */
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{ "Scalar FP ", "fpsimd", 0x0e000000, 0x0e000000, COUNT_CLASS},
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/* Unclassified */
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{ "Unclassified", "unclas", 0x00000000, 0x00000000, COUNT_CLASS},
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};
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static InsnClassExecCount sparc32_insn_classes[] = {
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{ "Call", "call", 0xc0000000, 0x40000000, COUNT_CLASS},
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{ "Branch ICond", "bcc", 0xc1c00000, 0x00800000, COUNT_CLASS},
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{ "Branch Fcond", "fbcc", 0xc1c00000, 0x01800000, COUNT_CLASS},
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{ "SetHi", "sethi", 0xc1c00000, 0x01000000, COUNT_CLASS},
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{ "FPU ALU", "fpu", 0xc1f00000, 0x81a00000, COUNT_CLASS},
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{ "ALU", "alu", 0xc0000000, 0x80000000, COUNT_CLASS},
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{ "Load/Store", "ldst", 0xc0000000, 0xc0000000, COUNT_CLASS},
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/* Unclassified */
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{ "Unclassified", "unclas", 0x00000000, 0x00000000, COUNT_INDIVIDUAL},
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};
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static InsnClassExecCount sparc64_insn_classes[] = {
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{ "SetHi & Branches", "op0", 0xc0000000, 0x00000000, COUNT_CLASS},
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{ "Call", "op1", 0xc0000000, 0x40000000, COUNT_CLASS},
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{ "Arith/Logical/Move", "op2", 0xc0000000, 0x80000000, COUNT_CLASS},
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{ "Arith/Logical/Move", "op3", 0xc0000000, 0xc0000000, COUNT_CLASS},
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/* Unclassified */
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{ "Unclassified", "unclas", 0x00000000, 0x00000000, COUNT_INDIVIDUAL},
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};
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/* Default matcher for currently unclassified architectures */
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static InsnClassExecCount default_insn_classes[] = {
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{ "Unclassified", "unclas", 0x00000000, 0x00000000, COUNT_INDIVIDUAL},
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};
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typedef struct {
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const char *qemu_target;
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InsnClassExecCount *table;
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int table_sz;
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} ClassSelector;
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static ClassSelector class_tables[] =
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{
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{ "aarch64", aarch64_insn_classes, ARRAY_SIZE(aarch64_insn_classes) },
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{ "sparc", sparc32_insn_classes, ARRAY_SIZE(sparc32_insn_classes) },
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{ "sparc64", sparc64_insn_classes, ARRAY_SIZE(sparc64_insn_classes) },
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{ NULL, default_insn_classes, ARRAY_SIZE(default_insn_classes) },
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};
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static InsnClassExecCount *class_table;
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static int class_table_sz;
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static gint cmp_exec_count(gconstpointer a, gconstpointer b)
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{
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InsnExecCount *ea = (InsnExecCount *) a;
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InsnExecCount *eb = (InsnExecCount *) b;
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return ea->count > eb->count ? -1 : 1;
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}
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static void plugin_exit(qemu_plugin_id_t id, void *p)
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{
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g_autoptr(GString) report = g_string_new("Instruction Classes:\n");
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int i;
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GList *counts;
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InsnClassExecCount *class = NULL;
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for (i = 0; i < class_table_sz; i++) {
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class = &class_table[i];
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switch (class->what) {
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case COUNT_CLASS:
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if (class->count || verbose) {
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g_string_append_printf(report, "Class: %-24s\t(%ld hits)\n",
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class->class,
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class->count);
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}
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break;
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case COUNT_INDIVIDUAL:
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g_string_append_printf(report, "Class: %-24s\tcounted individually\n",
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class->class);
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break;
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case COUNT_NONE:
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g_string_append_printf(report, "Class: %-24s\tnot counted\n",
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class->class);
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break;
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default:
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break;
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}
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}
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counts = g_hash_table_get_values(insns);
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if (counts && g_list_next(counts)) {
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GList *it;
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g_string_append_printf(report,"Individual Instructions:\n");
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it = g_list_sort(counts, cmp_exec_count);
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for (i = 0; i < limit && it->next; i++, it = it->next) {
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InsnExecCount *rec = (InsnExecCount *) it->data;
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g_string_append_printf(report, "Instr: %-24s\t(%ld hits)\t(op=%#08x/%s)\n",
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rec->insn,
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rec->count,
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rec->opcode,
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rec->class ?
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rec->class->class : "un-categorised");
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}
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g_list_free(it);
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}
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qemu_plugin_outs(report->str);
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}
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static void plugin_init(void)
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{
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insns = g_hash_table_new(NULL, g_direct_equal);
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}
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static void vcpu_insn_exec_before(unsigned int cpu_index, void *udata)
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{
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uint64_t *count = (uint64_t *) udata;
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(*count)++;
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}
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static uint64_t * find_counter(struct qemu_plugin_insn *insn)
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{
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int i;
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uint64_t *cnt = NULL;
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uint32_t opcode;
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InsnClassExecCount *class = NULL;
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/*
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* We only match the first 32 bits of the instruction which is
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* fine for most RISCs but a bit limiting for CISC architectures.
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* They would probably benefit from a more tailored plugin.
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* However we can fall back to individual instruction counting.
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*/
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opcode = *((uint32_t *)qemu_plugin_insn_data(insn));
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for (i = 0; !cnt && i < class_table_sz; i++) {
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class = &class_table[i];
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uint32_t masked_bits = opcode & class->mask;
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if (masked_bits == class->pattern) {
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break;
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}
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}
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g_assert(class);
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switch (class->what) {
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case COUNT_NONE:
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return NULL;
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case COUNT_CLASS:
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return &class->count;
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case COUNT_INDIVIDUAL:
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{
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InsnExecCount *icount;
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g_mutex_lock(&lock);
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icount = (InsnExecCount *) g_hash_table_lookup(insns,
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GUINT_TO_POINTER(opcode));
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if (!icount) {
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icount = g_new0(InsnExecCount, 1);
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icount->opcode = opcode;
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icount->insn = qemu_plugin_insn_disas(insn);
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icount->class = class;
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g_hash_table_insert(insns, GUINT_TO_POINTER(opcode),
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(gpointer) icount);
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}
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g_mutex_unlock(&lock);
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return &icount->count;
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}
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default:
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g_assert_not_reached();
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}
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return NULL;
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}
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static void vcpu_tb_trans(qemu_plugin_id_t id, struct qemu_plugin_tb *tb)
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{
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size_t n = qemu_plugin_tb_n_insns(tb);
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size_t i;
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for (i = 0; i < n; i++) {
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uint64_t *cnt;
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struct qemu_plugin_insn *insn = qemu_plugin_tb_get_insn(tb, i);
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cnt = find_counter(insn);
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if (cnt) {
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if (do_inline) {
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qemu_plugin_register_vcpu_insn_exec_inline(
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insn, QEMU_PLUGIN_INLINE_ADD_U64, cnt, 1);
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} else {
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qemu_plugin_register_vcpu_insn_exec_cb(
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insn, vcpu_insn_exec_before, QEMU_PLUGIN_CB_NO_REGS, cnt);
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}
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}
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}
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}
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QEMU_PLUGIN_EXPORT int qemu_plugin_install(qemu_plugin_id_t id,
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const qemu_info_t *info,
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int argc, char **argv)
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{
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int i;
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/* Select a class table appropriate to the guest architecture */
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for (i = 0; i < ARRAY_SIZE(class_tables); i++) {
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ClassSelector *entry = &class_tables[i];
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if (!entry->qemu_target ||
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strcmp(entry->qemu_target, info->target_name) == 0) {
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class_table = entry->table;
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class_table_sz = entry->table_sz;
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break;
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}
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}
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for (i = 0; i < argc; i++) {
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char *p = argv[i];
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if (strcmp(p, "inline") == 0) {
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do_inline = true;
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} else if (strcmp(p, "verbose") == 0) {
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verbose = true;
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} else {
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int j;
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CountType type = COUNT_INDIVIDUAL;
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if (*p == '!') {
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type = COUNT_NONE;
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p++;
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}
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for (j = 0; j < class_table_sz; j++) {
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if (strcmp(p, class_table[j].opt) == 0) {
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class_table[j].what = type;
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break;
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}
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}
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}
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}
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plugin_init();
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qemu_plugin_register_vcpu_tb_trans_cb(id, vcpu_tb_trans);
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qemu_plugin_register_atexit_cb(id, plugin_exit, NULL);
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return 0;
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}
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