tcg/riscv: Rationalize args to tcg_out_qemu_{ld,st}
Interpret the variable argument placement in the caller. Pass data_type instead of is64 -- there are several places where we already convert back from bool to type. Clean things up by using type throughout. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -1087,7 +1087,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
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#endif /* CONFIG_SOFTMMU */
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static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg val,
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TCGReg base, MemOp opc, bool is_64)
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TCGReg base, MemOp opc, TCGType type)
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{
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/* Byte swapping is left to middle-end expansion. */
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tcg_debug_assert((opc & MO_BSWAP) == 0);
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@ -1106,7 +1106,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg val,
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tcg_out_opc_imm(s, OPC_LH, val, base, 0);
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break;
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case MO_UL:
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if (is_64) {
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if (type == TCG_TYPE_I64) {
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tcg_out_opc_imm(s, OPC_LWU, val, base, 0);
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break;
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}
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@ -1122,30 +1122,21 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg val,
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}
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}
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static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
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static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
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MemOpIdx oi, TCGType data_type)
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{
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TCGReg addr_reg, data_reg;
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MemOpIdx oi;
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MemOp opc;
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#if defined(CONFIG_SOFTMMU)
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tcg_insn_unit *label_ptr[1];
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#else
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unsigned a_bits;
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#endif
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MemOp opc = get_memop(oi);
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TCGReg base;
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data_reg = *args++;
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addr_reg = *args++;
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oi = *args++;
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opc = get_memop(oi);
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#if defined(CONFIG_SOFTMMU)
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tcg_insn_unit *label_ptr[1];
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base = tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 1);
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tcg_out_qemu_ld_direct(s, data_reg, base, opc, is_64);
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add_qemu_ldst_label(s, 1, oi, (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
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data_reg, addr_reg, s->code_ptr, label_ptr);
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tcg_out_qemu_ld_direct(s, data_reg, base, opc, data_type);
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add_qemu_ldst_label(s, true, oi, data_type, data_reg, addr_reg,
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s->code_ptr, label_ptr);
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#else
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a_bits = get_alignment_bits(opc);
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unsigned a_bits = get_alignment_bits(opc);
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if (a_bits) {
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tcg_out_test_alignment(s, true, addr_reg, a_bits);
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}
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@ -1158,7 +1149,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
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tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_GUEST_BASE_REG, base);
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base = TCG_REG_TMP0;
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}
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tcg_out_qemu_ld_direct(s, data_reg, base, opc, is_64);
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tcg_out_qemu_ld_direct(s, data_reg, base, opc, data_type);
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#endif
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}
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@ -1186,30 +1177,21 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg val,
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}
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}
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static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
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static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
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MemOpIdx oi, TCGType data_type)
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{
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TCGReg addr_reg, data_reg;
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MemOpIdx oi;
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MemOp opc;
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#if defined(CONFIG_SOFTMMU)
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tcg_insn_unit *label_ptr[1];
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#else
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unsigned a_bits;
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#endif
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MemOp opc = get_memop(oi);
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TCGReg base;
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data_reg = *args++;
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addr_reg = *args++;
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oi = *args++;
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opc = get_memop(oi);
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#if defined(CONFIG_SOFTMMU)
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tcg_insn_unit *label_ptr[1];
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base = tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 0);
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tcg_out_qemu_st_direct(s, data_reg, base, opc);
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add_qemu_ldst_label(s, 0, oi, (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
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data_reg, addr_reg, s->code_ptr, label_ptr);
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add_qemu_ldst_label(s, false, oi, data_type, data_reg, addr_reg,
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s->code_ptr, label_ptr);
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#else
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a_bits = get_alignment_bits(opc);
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unsigned a_bits = get_alignment_bits(opc);
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if (a_bits) {
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tcg_out_test_alignment(s, false, addr_reg, a_bits);
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}
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@ -1508,16 +1490,16 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
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break;
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case INDEX_op_qemu_ld_i32:
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tcg_out_qemu_ld(s, args, false);
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tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32);
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break;
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case INDEX_op_qemu_ld_i64:
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tcg_out_qemu_ld(s, args, true);
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tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64);
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break;
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case INDEX_op_qemu_st_i32:
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tcg_out_qemu_st(s, args, false);
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tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32);
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break;
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case INDEX_op_qemu_st_i64:
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tcg_out_qemu_st(s, args, true);
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tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64);
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break;
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case INDEX_op_extrh_i64_i32:
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