mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

bulk: Do not declare function prototypes using 'extern' keyword

Browse Source 
By default, C function prototypes declared in headers are visible,
so there is no need to declare them as 'extern' functions.
Remove this redundancy in a single bulk commit; do not modify:

  - meson.build (used to check function availability at runtime)
  - pc-bios/
  - libdecnumber/
  - tests/
  - *.c

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20230605175647.88395-5-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2023-03-20 14:21:29 +01:00
parent a7041adce0
commit f703f1ef99
20 changed files with 79 additions and 86 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
bsd-user/bsd-file.h
View File

@ -51,10 +51,8 @@ do { \
unlock_user(p1, arg1, 0); \
} while (0)
extern struct iovec *lock_iovec(int type, abi_ulong target_addr, int count,
int copy);
extern void unlock_iovec(struct iovec *vec, abi_ulong target_addr, int count,
int copy);
struct iovec *lock_iovec(int type, abi_ulong target_addr, int count, int copy);
void unlock_iovec(struct iovec *vec, abi_ulong target_addr, int count, int copy);
int safe_open(const char *path, int flags, mode_t mode);
int safe_openat(int fd, const char *path, int flags, mode_t mode);

13
crypto/hmacpriv.h
View File

@ -28,19 +28,18 @@ struct QCryptoHmacDriver {
void (*hmac_free)(QCryptoHmac *hmac);
};
extern void *qcrypto_hmac_ctx_new(QCryptoHashAlgorithm alg,
const uint8_t *key, size_t nkey,
Error **errp);
void *qcrypto_hmac_ctx_new(QCryptoHashAlgorithm alg,
const uint8_t *key, size_t nkey,
Error **errp);
extern QCryptoHmacDriver qcrypto_hmac_lib_driver;
#ifdef CONFIG_AF_ALG
#include "afalgpriv.h"
extern QCryptoAFAlg *
qcrypto_afalg_hmac_ctx_new(QCryptoHashAlgorithm alg,
const uint8_t *key, size_t nkey,
Error **errp);
QCryptoAFAlg *qcrypto_afalg_hmac_ctx_new(QCryptoHashAlgorithm alg,
const uint8_t *key, size_t nkey,
Error **errp);
extern QCryptoHmacDriver qcrypto_hmac_afalg_driver;
#endif

8
hw/xen/xen_pt.h
View File

@ -340,11 +340,9 @@ static inline bool xen_pt_has_msix_mapping(XenPCIPassthroughState *s, int bar)
return s->msix && s->msix->bar_index == bar;
}
extern void *pci_assign_dev_load_option_rom(PCIDevice *dev,
int *size,
unsigned int domain,
unsigned int bus, unsigned int slot,
unsigned int function);
void *pci_assign_dev_load_option_rom(PCIDevice *dev, int *size,
unsigned int domain, unsigned int bus,
unsigned int slot, unsigned int function);
static inline bool is_igd_vga_passthrough(XenHostPCIDevice *dev)
{
return (xen_igd_gfx_pt_enabled()

14
include/crypto/secret_common.h
View File

@ -48,13 +48,11 @@ struct QCryptoSecretCommonClass {
};
extern int qcrypto_secret_lookup(const char *secretid,
uint8_t **data,
size_t *datalen,
Error **errp);
extern char *qcrypto_secret_lookup_as_utf8(const char *secretid,
Error **errp);
extern char *qcrypto_secret_lookup_as_base64(const char *secretid,
Error **errp);
int qcrypto_secret_lookup(const char *secretid,
uint8_t **data,
size_t *datalen,
Error **errp);
char *qcrypto_secret_lookup_as_utf8(const char *secretid, Error **errp);
char *qcrypto_secret_lookup_as_base64(const char *secretid, Error **errp);
#endif /* QCRYPTO_SECRET_COMMON_H */

42
include/exec/memory_ldst.h.inc
View File

@ -20,48 +20,48 @@
*/
#ifdef TARGET_ENDIANNESS
extern uint16_t glue(address_space_lduw, SUFFIX)(ARG1_DECL,
uint16_t glue(address_space_lduw, SUFFIX)(ARG1_DECL,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
extern uint32_t glue(address_space_ldl, SUFFIX)(ARG1_DECL,
uint32_t glue(address_space_ldl, SUFFIX)(ARG1_DECL,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
extern uint64_t glue(address_space_ldq, SUFFIX)(ARG1_DECL,
uint64_t glue(address_space_ldq, SUFFIX)(ARG1_DECL,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
extern void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL,
void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL,
hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result);
extern void glue(address_space_stw, SUFFIX)(ARG1_DECL,
void glue(address_space_stw, SUFFIX)(ARG1_DECL,
hwaddr addr, uint16_t val, MemTxAttrs attrs, MemTxResult *result);
extern void glue(address_space_stl, SUFFIX)(ARG1_DECL,
void glue(address_space_stl, SUFFIX)(ARG1_DECL,
hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result);
extern void glue(address_space_stq, SUFFIX)(ARG1_DECL,
void glue(address_space_stq, SUFFIX)(ARG1_DECL,
hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result);
#else
extern uint8_t glue(address_space_ldub, SUFFIX)(ARG1_DECL,
uint8_t glue(address_space_ldub, SUFFIX)(ARG1_DECL,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
extern uint16_t glue(address_space_lduw_le, SUFFIX)(ARG1_DECL,
uint16_t glue(address_space_lduw_le, SUFFIX)(ARG1_DECL,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
extern uint16_t glue(address_space_lduw_be, SUFFIX)(ARG1_DECL,
uint16_t glue(address_space_lduw_be, SUFFIX)(ARG1_DECL,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
extern uint32_t glue(address_space_ldl_le, SUFFIX)(ARG1_DECL,
uint32_t glue(address_space_ldl_le, SUFFIX)(ARG1_DECL,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
extern uint32_t glue(address_space_ldl_be, SUFFIX)(ARG1_DECL,
uint32_t glue(address_space_ldl_be, SUFFIX)(ARG1_DECL,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
extern uint64_t glue(address_space_ldq_le, SUFFIX)(ARG1_DECL,
uint64_t glue(address_space_ldq_le, SUFFIX)(ARG1_DECL,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
extern uint64_t glue(address_space_ldq_be, SUFFIX)(ARG1_DECL,
uint64_t glue(address_space_ldq_be, SUFFIX)(ARG1_DECL,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
extern void glue(address_space_stb, SUFFIX)(ARG1_DECL,
void glue(address_space_stb, SUFFIX)(ARG1_DECL,
hwaddr addr, uint8_t val, MemTxAttrs attrs, MemTxResult *result);
extern void glue(address_space_stw_le, SUFFIX)(ARG1_DECL,
void glue(address_space_stw_le, SUFFIX)(ARG1_DECL,
hwaddr addr, uint16_t val, MemTxAttrs attrs, MemTxResult *result);
extern void glue(address_space_stw_be, SUFFIX)(ARG1_DECL,
void glue(address_space_stw_be, SUFFIX)(ARG1_DECL,
hwaddr addr, uint16_t val, MemTxAttrs attrs, MemTxResult *result);
extern void glue(address_space_stl_le, SUFFIX)(ARG1_DECL,
void glue(address_space_stl_le, SUFFIX)(ARG1_DECL,
hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result);
extern void glue(address_space_stl_be, SUFFIX)(ARG1_DECL,
void glue(address_space_stl_be, SUFFIX)(ARG1_DECL,
hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result);
extern void glue(address_space_stq_le, SUFFIX)(ARG1_DECL,
void glue(address_space_stq_le, SUFFIX)(ARG1_DECL,
hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result);
extern void glue(address_space_stq_be, SUFFIX)(ARG1_DECL,
void glue(address_space_stq_be, SUFFIX)(ARG1_DECL,
hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result);
#endif

4
include/exec/page-vary.h
View File

@ -27,8 +27,8 @@ typedef struct {
} TargetPageBits;
#ifdef IN_PAGE_VARY
extern bool set_preferred_target_page_bits_common(int bits);
extern void finalize_target_page_bits_common(int min);
bool set_preferred_target_page_bits_common(int bits);
void finalize_target_page_bits_common(int min);
#endif
/**

2
include/hw/misc/aspeed_scu.h
View File

@ -51,7 +51,7 @@ struct AspeedSCUState {
#define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04)
extern bool is_supported_silicon_rev(uint32_t silicon_rev);
bool is_supported_silicon_rev(uint32_t silicon_rev);
struct AspeedSCUClass {

4
include/hw/nvram/npcm7xx_otp.h
View File

@ -73,7 +73,7 @@ typedef struct NPCM7xxOTPClass NPCM7xxOTPClass;
* Each nibble of data is encoded into a byte, so the number of bytes written
* to the array will be @len * 2.
*/
extern void npcm7xx_otp_array_write(NPCM7xxOTPState *s, const void *data,
unsigned int offset, unsigned int len);
void npcm7xx_otp_array_write(NPCM7xxOTPState *s, const void *data,
unsigned int offset, unsigned int len);
#endif /* NPCM7XX_OTP_H */

4
include/hw/qdev-core.h
View File

@ -1086,7 +1086,7 @@ typedef enum MachineInitPhase {
PHASE_MACHINE_READY,
} MachineInitPhase;
extern bool phase_check(MachineInitPhase phase);
extern void phase_advance(MachineInitPhase phase);
bool phase_check(MachineInitPhase phase);
void phase_advance(MachineInitPhase phase);
#endif

4
include/qemu/crc-ccitt.h
View File

@ -17,8 +17,8 @@
extern uint16_t const crc_ccitt_table[256];
extern uint16_t const crc_ccitt_false_table[256];
extern uint16_t crc_ccitt(uint16_t crc, const uint8_t *buffer, size_t len);
extern uint16_t crc_ccitt_false(uint16_t crc, const uint8_t *buffer, size_t len);
uint16_t crc_ccitt(uint16_t crc, const uint8_t *buffer, size_t len);
uint16_t crc_ccitt_false(uint16_t crc, const uint8_t *buffer, size_t len);
static inline uint16_t crc_ccitt_byte(uint16_t crc, const uint8_t c)
{

4
include/qemu/osdep.h
View File

@ -250,7 +250,7 @@ extern "C" {
* supports QEMU_ERROR, this will be reported at compile time; otherwise
* this will be reported at link time due to the missing symbol.
*/
G_NORETURN extern
G_NORETURN
void QEMU_ERROR("code path is reachable")
qemu_build_not_reached_always(void);
#if defined(__OPTIMIZE__) && !defined(__NO_INLINE__)
@ -506,7 +506,7 @@ void qemu_anon_ram_free(void *ptr, size_t size);
* See MySQL bug #7156 (http://bugs.mysql.com/bug.php?id=7156) for discussion
* about Solaris missing the madvise() prototype.
*/
extern int madvise(char *, size_t, int);
int madvise(char *, size_t, int);
#endif
#if defined(CONFIG_LINUX)

14
include/qemu/rcu.h
View File

@ -118,19 +118,19 @@ static inline void rcu_read_unlock(void)
}
}
extern void synchronize_rcu(void);
void synchronize_rcu(void);
/*
* Reader thread registration.
*/
extern void rcu_register_thread(void);
extern void rcu_unregister_thread(void);
void rcu_register_thread(void);
void rcu_unregister_thread(void);
/*
* Support for fork(). fork() support is enabled at startup.
*/
extern void rcu_enable_atfork(void);
extern void rcu_disable_atfork(void);
void rcu_enable_atfork(void);
void rcu_disable_atfork(void);
struct rcu_head;
typedef void RCUCBFunc(struct rcu_head *head);
@ -140,8 +140,8 @@ struct rcu_head {
RCUCBFunc *func;
};
extern void call_rcu1(struct rcu_head *head, RCUCBFunc *func);
extern void drain_call_rcu(void);
void call_rcu1(struct rcu_head *head, RCUCBFunc *func);
void drain_call_rcu(void);
/* The operands of the minus operator must have the same type,
* which must be the one that we specify in the cast.

4
include/qemu/sys_membarrier.h
View File

@ -14,8 +14,8 @@
* side. The slow side forces processor-level ordering on all other cores
* through a system call.
*/
extern void smp_mb_global_init(void);
extern void smp_mb_global(void);
void smp_mb_global_init(void);
void smp_mb_global(void);
#define smp_mb_placeholder() barrier()
#else
/* Keep it simple, execute a real memory barrier on both sides. */

6
include/qemu/uri.h
View File

@ -96,8 +96,8 @@ typedef struct QueryParams {
QueryParam *p; /* array of parameters */
} QueryParams;
QueryParams *query_params_new (int init_alloc);
extern QueryParams *query_params_parse (const char *query);
extern void query_params_free (QueryParams *ps);
QueryParams *query_params_new(int init_alloc);
QueryParams *query_params_parse(const char *query);
void query_params_free(QueryParams *ps);
#endif /* QEMU_URI_H */

14
include/sysemu/accel-blocker.h
View File

@ -16,7 +16,7 @@
#include "sysemu/cpus.h"
extern void accel_blocker_init(void);
void accel_blocker_init(void);
/*
* accel_{cpu_}ioctl_begin/end:
@ -26,10 +26,10 @@ extern void accel_blocker_init(void);
* called, preventing new ioctls to run. They will continue only after
* accel_ioctl_inibith_end().
*/
extern void accel_ioctl_begin(void);
extern void accel_ioctl_end(void);
extern void accel_cpu_ioctl_begin(CPUState *cpu);
extern void accel_cpu_ioctl_end(CPUState *cpu);
void accel_ioctl_begin(void);
void accel_ioctl_end(void);
void accel_cpu_ioctl_begin(CPUState *cpu);
void accel_cpu_ioctl_end(CPUState *cpu);
/*
* accel_ioctl_inhibit_begin: start critical section
@ -42,7 +42,7 @@ extern void accel_cpu_ioctl_end(CPUState *cpu);
* This allows the caller to access shared data or perform operations without
* worrying of concurrent vcpus accesses.
*/
extern void accel_ioctl_inhibit_begin(void);
void accel_ioctl_inhibit_begin(void);
/*
* accel_ioctl_inhibit_end: end critical section started by
@ -50,6 +50,6 @@ extern void accel_ioctl_inhibit_begin(void);
*
* This function allows blocked accel_{cpu_}ioctl_begin() to continue.
*/
extern void accel_ioctl_inhibit_end(void);
void accel_ioctl_inhibit_end(void);
#endif /* ACCEL_BLOCKER_H */

4
include/sysemu/os-win32.h
View File

@ -66,8 +66,8 @@ extern "C" {
* setjmp to _setjmpex instead. However, they are still defined in libmingwex.a,
* which gets linked automatically.
*/
extern int __mingw_setjmp(jmp_buf);
extern void __attribute__((noreturn)) __mingw_longjmp(jmp_buf, int);
int __mingw_setjmp(jmp_buf);
void __attribute__((noreturn)) __mingw_longjmp(jmp_buf, int);
#define setjmp(env) __mingw_setjmp(env)
#define longjmp(env, val) __mingw_longjmp(env, val)
#elif defined(_WIN64)

4
include/user/safe-syscall.h
View File

@ -126,8 +126,8 @@
*/
/* The core part of this function is implemented in assembly */
extern long safe_syscall_base(int *pending, long number, ...);
extern long safe_syscall_set_errno_tail(int value);
long safe_syscall_base(int *pending, long number, ...);
long safe_syscall_set_errno_tail(int value);
/* These are defined by the safe-syscall.inc.S file */
extern char safe_syscall_start[];

6
target/i386/sev.h
View File

@ -46,9 +46,9 @@ bool sev_es_enabled(void);
#define sev_es_enabled() 0
#endif
extern uint32_t sev_get_cbit_position(void);
extern uint32_t sev_get_reduced_phys_bits(void);
extern bool sev_add_kernel_loader_hashes(SevKernelLoaderContext *ctx, Error **errp);
uint32_t sev_get_cbit_position(void);
uint32_t sev_get_reduced_phys_bits(void);
bool sev_add_kernel_loader_hashes(SevKernelLoaderContext *ctx, Error **errp);
int sev_encrypt_flash(uint8_t *ptr, uint64_t len, Error **errp);
int sev_inject_launch_secret(const char *hdr, const char *secret,

4
target/mips/cpu.h
View File

@ -1224,8 +1224,8 @@ void mips_cpu_list(void);
#define cpu_list mips_cpu_list
extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env);
extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env);
void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env);
uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env);
/*
* MMU modes definitions. We carefully match the indices with our

4
tcg/tcg-internal.h
View File

@ -64,8 +64,8 @@ static inline TCGv_i32 TCGV_HIGH(TCGv_i64 t)
return temp_tcgv_i32(tcgv_i64_temp(t) + !HOST_BIG_ENDIAN);
}
#else
extern TCGv_i32 TCGV_LOW(TCGv_i64) QEMU_ERROR("32-bit code path is reachable");
extern TCGv_i32 TCGV_HIGH(TCGv_i64) QEMU_ERROR("32-bit code path is reachable");
TCGv_i32 TCGV_LOW(TCGv_i64) QEMU_ERROR("32-bit code path is reachable");
TCGv_i32 TCGV_HIGH(TCGv_i64) QEMU_ERROR("32-bit code path is reachable");
#endif
static inline TCGv_i64 TCGV128_LOW(TCGv_i128 t)