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Merge remote-tracking branch 'mjt/trivial-patches-next' into staging

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# By Dong Xu Wang (2) and others
# Via Michael Tokarev
* mjt/trivial-patches-next:
  osdep.h: include sys/types.h for ssize_t definition
  remove double semicolons
  clean unnecessary code: don't check g_strdup arg for NULL
  docs: mention AddressSpaces in docs/memory.txt
  audio: update documentation after removing --audio-card-list option
  m25p80.c: Sync Flash chip list with Linux
  bsd-user: OS-agnostic 64-bit SYSCTL types

Message-id: 518F61B9.9050803@msgid.tls.msk.ru
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Anthony Liguori 2013-05-13 09:44:25 -05:00
commit f6e136e47a
14 changed files with 49 additions and 28 deletions
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2
block/nbd.c
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@ -609,7 +609,7 @@ static int nbd_co_discard(BlockDriverState *bs, int64_t sector_num,
return 0;
}
request.type = NBD_CMD_TRIM;
request.from = sector_num * 512;;
request.from = sector_num * 512;
request.len = nb_sectors * 512;
nbd_coroutine_start(s, &request);

7
bsd-user/syscall.c
View File

@ -211,10 +211,11 @@ static int sysctl_oldcvt(void *holdp, size_t holdlen, uint32_t kind)
*(uint64_t *)holdp = tswap64(*(unsigned long *)holdp);
break;
#endif
#if !defined(__FreeBSD_version) || __FreeBSD_version < 900031
case CTLTYPE_QUAD:
#else
#ifdef CTLTYPE_U64
case CTLTYPE_S64:
case CTLTYPE_U64:
#else
case CTLTYPE_QUAD:
#endif
*(uint64_t *)holdp = tswap64(*(uint64_t *)holdp);
break;

11
docs/memory.txt
View File

@ -15,10 +15,13 @@ The memory model provides support for
- setting up coalesced memory for kvm
- setting up ioeventfd regions for kvm
Memory is modelled as a tree (really acyclic graph) of MemoryRegion objects.
The root of the tree is memory as seen from the CPU's viewpoint (the system
bus). Nodes in the tree represent other buses, memory controllers, and
memory regions that have been rerouted. Leaves are RAM and MMIO regions.
Memory is modelled as an acyclic graph of MemoryRegion objects. Sinks
(leaves) are RAM and MMIO regions, while other nodes represent
buses, memory controllers, and memory regions that have been rerouted.
In addition to MemoryRegion objects, the memory API provides AddressSpace
objects for every root and possibly for intermediate MemoryRegions too.
These represent memory as seen from the CPU or a device's viewpoint.
Types of regions
----------------

4
fsdev/virtfs-proxy-helper.c
View File

@ -248,7 +248,7 @@ static int send_fd(int sockfd, int fd)
static int send_status(int sockfd, struct iovec *iovec, int status)
{
ProxyHeader header;
int retval, msg_size;;
int retval, msg_size;
if (status < 0) {
header.type = T_ERROR;
@ -381,7 +381,7 @@ static int send_response(int sock, struct iovec *iovec, int size)
proxy_marshal(iovec, 0, "dd", header.type, header.size);
retval = socket_write(sock, iovec->iov_base, header.size + PROXY_HDR_SZ);
if (retval < 0) {
return retval;;
return retval;
}
return 0;
}

2
hw/9pfs/virtio-9p-local.c
View File

@ -878,7 +878,7 @@ static int local_remove(FsContext *ctx, const char *path)
* Now remove the name from parent directory
* .virtfs_metadata directory
*/
err = remove(local_mapped_attr_path(ctx, path, buffer));;
err = remove(local_mapped_attr_path(ctx, path, buffer));
if (err < 0 && errno != ENOENT) {
/*
* We didn't had the .virtfs_metadata file. May be file created

31
hw/block/m25p80.c
View File

@ -91,18 +91,27 @@ static const FlashPartInfo known_devices[] = {
{ INFO("at26df161a", 0x1f4601, 0, 64 << 10, 32, ER_4K) },
{ INFO("at26df321", 0x1f4700, 0, 64 << 10, 64, ER_4K) },
{ INFO("at45db081d", 0x1f2500, 0, 64 << 10, 16, ER_4K) },
/* EON -- en25xxx */
{ INFO("en25f32", 0x1c3116, 0, 64 << 10, 64, ER_4K) },
{ INFO("en25p32", 0x1c2016, 0, 64 << 10, 64, 0) },
{ INFO("en25q32b", 0x1c3016, 0, 64 << 10, 64, 0) },
{ INFO("en25p64", 0x1c2017, 0, 64 << 10, 128, 0) },
{ INFO("en25q64", 0x1c3017, 0, 64 << 10, 128, ER_4K) },
/* GigaDevice */
{ INFO("gd25q32", 0xc84016, 0, 64 << 10, 64, ER_4K) },
{ INFO("gd25q64", 0xc84017, 0, 64 << 10, 128, ER_4K) },
/* Intel/Numonyx -- xxxs33b */
{ INFO("160s33b", 0x898911, 0, 64 << 10, 32, 0) },
{ INFO("320s33b", 0x898912, 0, 64 << 10, 64, 0) },
{ INFO("640s33b", 0x898913, 0, 64 << 10, 128, 0) },
{ INFO("n25q064", 0x20ba17, 0, 64 << 10, 128, 0) },
/* Macronix */
{ INFO("mx25l2005a", 0xc22012, 0, 64 << 10, 4, ER_4K) },
{ INFO("mx25l4005a", 0xc22013, 0, 64 << 10, 8, ER_4K) },
{ INFO("mx25l8005", 0xc22014, 0, 64 << 10, 16, 0) },
{ INFO("mx25l1606e", 0xc22015, 0, 64 << 10, 32, ER_4K) },
@ -113,15 +122,16 @@ static const FlashPartInfo known_devices[] = {
{ INFO("mx25l25635e", 0xc22019, 0, 64 << 10, 512, 0) },
{ INFO("mx25l25655e", 0xc22619, 0, 64 << 10, 512, 0) },
/* Micron */
{ INFO("n25q128a11", 0x20bb18, 0, 64 << 10, 256, 0) },
{ INFO("n25q128a13", 0x20ba18, 0, 64 << 10, 256, 0) },
{ INFO("n25q256a", 0x20ba19, 0, 64 << 10, 512, ER_4K) },
/* Spansion -- single (large) sector size only, at least
* for the chips listed here (without boot sectors).
*/
{ INFO("s25sl004a", 0x010212, 0, 64 << 10, 8, 0) },
{ INFO("s25sl008a", 0x010213, 0, 64 << 10, 16, 0) },
{ INFO("s25sl016a", 0x010214, 0, 64 << 10, 32, 0) },
{ INFO("s25sl032a", 0x010215, 0, 64 << 10, 64, 0) },
{ INFO("s25sl032p", 0x010215, 0x4d00, 64 << 10, 64, ER_4K) },
{ INFO("s25sl064a", 0x010216, 0, 64 << 10, 128, 0) },
{ INFO("s25sl064p", 0x010216, 0x4d00, 64 << 10, 128, ER_4K) },
{ INFO("s25fl256s0", 0x010219, 0x4d00, 256 << 10, 128, 0) },
{ INFO("s25fl256s1", 0x010219, 0x4d01, 64 << 10, 512, 0) },
{ INFO("s25fl512s", 0x010220, 0x4d00, 256 << 10, 256, 0) },
@ -130,6 +140,11 @@ static const FlashPartInfo known_devices[] = {
{ INFO("s25sl12801", 0x012018, 0x0301, 64 << 10, 256, 0) },
{ INFO("s25fl129p0", 0x012018, 0x4d00, 256 << 10, 64, 0) },
{ INFO("s25fl129p1", 0x012018, 0x4d01, 64 << 10, 256, 0) },
{ INFO("s25sl004a", 0x010212, 0, 64 << 10, 8, 0) },
{ INFO("s25sl008a", 0x010213, 0, 64 << 10, 16, 0) },
{ INFO("s25sl016a", 0x010214, 0, 64 << 10, 32, 0) },
{ INFO("s25sl032a", 0x010215, 0, 64 << 10, 64, 0) },
{ INFO("s25sl064a", 0x010216, 0, 64 << 10, 128, 0) },
{ INFO("s25fl016k", 0xef4015, 0, 64 << 10, 32, ER_4K | ER_32K) },
{ INFO("s25fl064k", 0xef4017, 0, 64 << 10, 128, ER_4K | ER_32K) },
@ -153,11 +168,13 @@ static const FlashPartInfo known_devices[] = {
{ INFO("m25p32", 0x202016, 0, 64 << 10, 64, 0) },
{ INFO("m25p64", 0x202017, 0, 64 << 10, 128, 0) },
{ INFO("m25p128", 0x202018, 0, 256 << 10, 64, 0) },
{ INFO("n25q032", 0x20ba16, 0, 64 << 10, 64, 0) },
{ INFO("m45pe10", 0x204011, 0, 64 << 10, 2, 0) },
{ INFO("m45pe80", 0x204014, 0, 64 << 10, 16, 0) },
{ INFO("m45pe16", 0x204015, 0, 64 << 10, 32, 0) },
{ INFO("m25pe20", 0x208012, 0, 64 << 10, 4, 0) },
{ INFO("m25pe80", 0x208014, 0, 64 << 10, 16, 0) },
{ INFO("m25pe16", 0x208015, 0, 64 << 10, 32, ER_4K) },
@ -174,8 +191,12 @@ static const FlashPartInfo known_devices[] = {
{ INFO("w25x16", 0xef3015, 0, 64 << 10, 32, ER_4K) },
{ INFO("w25x32", 0xef3016, 0, 64 << 10, 64, ER_4K) },
{ INFO("w25q32", 0xef4016, 0, 64 << 10, 64, ER_4K) },
{ INFO("w25q32dw", 0xef6016, 0, 64 << 10, 64, ER_4K) },
{ INFO("w25x64", 0xef3017, 0, 64 << 10, 128, ER_4K) },
{ INFO("w25q64", 0xef4017, 0, 64 << 10, 128, ER_4K) },
{ INFO("w25q80", 0xef5014, 0, 64 << 10, 16, ER_4K) },
{ INFO("w25q80bl", 0xef4014, 0, 64 << 10, 16, ER_4K) },
{ INFO("w25q256", 0xef4019, 0, 64 << 10, 512, ER_4K) },
/* Numonyx -- n25q128 */
{ INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) },

2
hw/i386/pc_q35.c
View File

@ -128,7 +128,7 @@ static void pc_q35_init(QEMUMachineInitArgs *args)
q35_host->mch.ram_memory = ram_memory;
q35_host->mch.pci_address_space = pci_memory;
q35_host->mch.system_memory = get_system_memory();
q35_host->mch.address_space_io = get_system_io();;
q35_host->mch.address_space_io = get_system_io();
q35_host->mch.below_4g_mem_size = below_4g_mem_size;
q35_host->mch.above_4g_mem_size = above_4g_mem_size;
/* pci */

2
hw/intc/imx_avic.c
View File

@ -370,7 +370,7 @@ static void imx_avic_reset(DeviceState *dev)
static int imx_avic_init(SysBusDevice *dev)
{
IMXAVICState *s = FROM_SYSBUS(IMXAVICState, dev);;
IMXAVICState *s = FROM_SYSBUS(IMXAVICState, dev);
memory_region_init_io(&s->iomem, &imx_avic_ops, s, "imx_avic", 0x1000);
sysbus_init_mmio(dev, &s->iomem);

4
hw/usb/host-linux.c
View File

@ -651,7 +651,7 @@ static void usb_host_handle_reset(USBDevice *dev)
trace_usb_host_reset(s->bus_num, s->addr);
usb_host_do_reset(s);;
usb_host_do_reset(s);
usb_host_claim_interfaces(s, 0);
usb_linux_update_endp_table(s);
@ -1429,7 +1429,7 @@ static void usb_host_exit_notifier(struct Notifier *n, void *data)
usb_host_release_port(s);
if (s->fd != -1) {
usb_host_do_reset(s);;
usb_host_do_reset(s);
}
}

2
include/qemu/osdep.h
View File

@ -5,8 +5,8 @@
#include <stdarg.h>
#include <stddef.h>
#include <stdbool.h>
#ifdef __OpenBSD__
#include <sys/types.h>
#ifdef __OpenBSD__
#include <sys/signal.h>
#endif

4
qemu-doc.texi
View File

@ -214,10 +214,6 @@ PCI UHCI USB controller and a virtual USB hub.
SMP is supported with up to 255 CPUs.
Note that adlib, gus and cs4231a are only available when QEMU was
configured with --audio-card-list option containing the name(s) of
required card(s).
QEMU uses the PC BIOS from the Bochs project and the Plex86/Bochs LGPL
VGA BIOS.

2
qga/channel-win32.c
View File

@ -268,7 +268,7 @@ static GIOStatus ga_channel_write(GAChannel *c, const char *buf, size_t size,
GIOStatus ga_channel_write_all(GAChannel *c, const char *buf, size_t size)
{
GIOStatus status = G_IO_STATUS_NORMAL;;
GIOStatus status = G_IO_STATUS_NORMAL;
size_t count;
while (size) {

2
util/uri.c
View File

@ -2162,7 +2162,7 @@ query_params_append (struct QueryParams *ps,
}
ps->p[ps->n].name = g_strdup(name);
ps->p[ps->n].value = value ? g_strdup(value) : NULL;
ps->p[ps->n].value = g_strdup(value);
ps->p[ps->n].ignore = 0;
ps->n++;

2
vl.c
View File

@ -1215,7 +1215,7 @@ void add_boot_device_path(int32_t bootindex, DeviceState *dev,
node = g_malloc0(sizeof(FWBootEntry));
node->bootindex = bootindex;
node->suffix = suffix ? g_strdup(suffix) : NULL;
node->suffix = g_strdup(suffix);
node->dev = dev;
QTAILQ_FOREACH(i, &fw_boot_order, link) {