target-mips: add MAAR, MAARI register
The MAAR register is a read/write register included in Release 5 of the architecture that defines the accessibility attributes of physical address regions. In particular, MAAR defines whether an instruction fetch or data load can speculatively access a memory region within the physical address bounds specified by MAAR. As QEMU doesn't do speculative access, hence this patch only provides ability to access the registers. Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
This commit is contained in:
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c98d3d79ee
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f6d4dd8109
@ -165,6 +165,7 @@ typedef struct mips_def_t mips_def_t;
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#define MIPS_FPU_MAX 1
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#define MIPS_FPU_MAX 1
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#define MIPS_DSP_ACC 4
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#define MIPS_DSP_ACC 4
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#define MIPS_KSCRATCH_NUM 6
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#define MIPS_KSCRATCH_NUM 6
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#define MIPS_MAAR_MAX 16 /* Must be an even number. */
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typedef struct TCState TCState;
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typedef struct TCState TCState;
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struct TCState {
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struct TCState {
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@ -483,10 +484,13 @@ struct CPUMIPSState {
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#define CP0C5_SBRI 6
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#define CP0C5_SBRI 6
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#define CP0C5_MVH 5
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#define CP0C5_MVH 5
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#define CP0C5_LLB 4
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#define CP0C5_LLB 4
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#define CP0C5_MRP 3
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#define CP0C5_UFR 2
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#define CP0C5_UFR 2
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#define CP0C5_NFExists 0
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#define CP0C5_NFExists 0
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int32_t CP0_Config6;
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int32_t CP0_Config6;
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int32_t CP0_Config7;
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int32_t CP0_Config7;
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uint64_t CP0_MAAR[MIPS_MAAR_MAX];
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int32_t CP0_MAARI;
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/* XXX: Maybe make LLAddr per-TC? */
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/* XXX: Maybe make LLAddr per-TC? */
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uint64_t lladdr;
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uint64_t lladdr;
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target_ulong llval;
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target_ulong llval;
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@ -77,6 +77,8 @@ DEF_HELPER_1(mftc0_epc, tl, env)
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DEF_HELPER_1(mftc0_ebase, tl, env)
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DEF_HELPER_1(mftc0_ebase, tl, env)
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DEF_HELPER_2(mftc0_configx, tl, env, tl)
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DEF_HELPER_2(mftc0_configx, tl, env, tl)
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DEF_HELPER_1(mfc0_lladdr, tl, env)
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DEF_HELPER_1(mfc0_lladdr, tl, env)
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DEF_HELPER_1(mfc0_maar, tl, env)
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DEF_HELPER_1(mfhc0_maar, tl, env)
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DEF_HELPER_2(mfc0_watchlo, tl, env, i32)
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DEF_HELPER_2(mfc0_watchlo, tl, env, i32)
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DEF_HELPER_2(mfc0_watchhi, tl, env, i32)
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DEF_HELPER_2(mfc0_watchhi, tl, env, i32)
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DEF_HELPER_1(mfc0_debug, tl, env)
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DEF_HELPER_1(mfc0_debug, tl, env)
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@ -88,6 +90,7 @@ DEF_HELPER_1(dmfc0_tccontext, tl, env)
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DEF_HELPER_1(dmfc0_tcschedule, tl, env)
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DEF_HELPER_1(dmfc0_tcschedule, tl, env)
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DEF_HELPER_1(dmfc0_tcschefback, tl, env)
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DEF_HELPER_1(dmfc0_tcschefback, tl, env)
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DEF_HELPER_1(dmfc0_lladdr, tl, env)
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DEF_HELPER_1(dmfc0_lladdr, tl, env)
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DEF_HELPER_1(dmfc0_maar, tl, env)
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DEF_HELPER_2(dmfc0_watchlo, tl, env, i32)
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DEF_HELPER_2(dmfc0_watchlo, tl, env, i32)
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#endif /* TARGET_MIPS64 */
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#endif /* TARGET_MIPS64 */
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@ -144,6 +147,9 @@ DEF_HELPER_2(mtc0_config3, void, env, tl)
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DEF_HELPER_2(mtc0_config4, void, env, tl)
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DEF_HELPER_2(mtc0_config4, void, env, tl)
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DEF_HELPER_2(mtc0_config5, void, env, tl)
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DEF_HELPER_2(mtc0_config5, void, env, tl)
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DEF_HELPER_2(mtc0_lladdr, void, env, tl)
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DEF_HELPER_2(mtc0_lladdr, void, env, tl)
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DEF_HELPER_2(mtc0_maar, void, env, tl)
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DEF_HELPER_2(mthc0_maar, void, env, tl)
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DEF_HELPER_2(mtc0_maari, void, env, tl)
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DEF_HELPER_3(mtc0_watchlo, void, env, tl, i32)
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DEF_HELPER_3(mtc0_watchlo, void, env, tl, i32)
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DEF_HELPER_3(mtc0_watchhi, void, env, tl, i32)
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DEF_HELPER_3(mtc0_watchhi, void, env, tl, i32)
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DEF_HELPER_2(mtc0_xcontext, void, env, tl)
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DEF_HELPER_2(mtc0_xcontext, void, env, tl)
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@ -204,8 +204,8 @@ const VMStateDescription vmstate_tlb = {
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const VMStateDescription vmstate_mips_cpu = {
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const VMStateDescription vmstate_mips_cpu = {
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.name = "cpu",
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.name = "cpu",
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.version_id = 7,
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.version_id = 8,
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.minimum_version_id = 7,
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.minimum_version_id = 8,
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.post_load = cpu_post_load,
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.post_load = cpu_post_load,
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.fields = (VMStateField[]) {
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.fields = (VMStateField[]) {
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/* Active TC */
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/* Active TC */
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@ -272,6 +272,8 @@ const VMStateDescription vmstate_mips_cpu = {
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VMSTATE_INT32(env.CP0_Config3, MIPSCPU),
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VMSTATE_INT32(env.CP0_Config3, MIPSCPU),
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VMSTATE_INT32(env.CP0_Config6, MIPSCPU),
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VMSTATE_INT32(env.CP0_Config6, MIPSCPU),
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VMSTATE_INT32(env.CP0_Config7, MIPSCPU),
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VMSTATE_INT32(env.CP0_Config7, MIPSCPU),
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VMSTATE_UINT64_ARRAY(env.CP0_MAAR, MIPSCPU, MIPS_MAAR_MAX),
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VMSTATE_INT32(env.CP0_MAARI, MIPSCPU),
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VMSTATE_UINT64(env.lladdr, MIPSCPU),
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VMSTATE_UINT64(env.lladdr, MIPSCPU),
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VMSTATE_UINTTL_ARRAY(env.CP0_WatchLo, MIPSCPU, 8),
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VMSTATE_UINTTL_ARRAY(env.CP0_WatchLo, MIPSCPU, 8),
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VMSTATE_INT32_ARRAY(env.CP0_WatchHi, MIPSCPU, 8),
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VMSTATE_INT32_ARRAY(env.CP0_WatchHi, MIPSCPU, 8),
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@ -889,6 +889,16 @@ target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
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return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
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return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
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}
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}
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target_ulong helper_mfc0_maar(CPUMIPSState *env)
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{
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return (int32_t) env->CP0_MAAR[env->CP0_MAARI];
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}
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target_ulong helper_mfhc0_maar(CPUMIPSState *env)
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{
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return env->CP0_MAAR[env->CP0_MAARI] >> 32;
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}
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target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
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target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
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{
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{
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return (int32_t)env->CP0_WatchLo[sel];
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return (int32_t)env->CP0_WatchLo[sel];
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@ -955,6 +965,11 @@ target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
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return env->lladdr >> env->CP0_LLAddr_shift;
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return env->lladdr >> env->CP0_LLAddr_shift;
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}
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}
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target_ulong helper_dmfc0_maar(CPUMIPSState *env)
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{
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return env->CP0_MAAR[env->CP0_MAARI];
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}
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target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
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target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
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{
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{
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return env->CP0_WatchLo[sel];
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return env->CP0_WatchLo[sel];
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@ -1578,6 +1593,36 @@ void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
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env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
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env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
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}
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}
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#define MTC0_MAAR_MASK(env) \
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((0x1ULL << 63) | ((env->PAMask >> 4) & ~0xFFFull) | 0x3)
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void helper_mtc0_maar(CPUMIPSState *env, target_ulong arg1)
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{
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env->CP0_MAAR[env->CP0_MAARI] = arg1 & MTC0_MAAR_MASK(env);
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}
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void helper_mthc0_maar(CPUMIPSState *env, target_ulong arg1)
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{
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env->CP0_MAAR[env->CP0_MAARI] =
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(((uint64_t) arg1 << 32) & MTC0_MAAR_MASK(env)) |
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(env->CP0_MAAR[env->CP0_MAARI] & 0x00000000ffffffffULL);
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}
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void helper_mtc0_maari(CPUMIPSState *env, target_ulong arg1)
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{
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int index = arg1 & 0x3f;
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if (index == 0x3f) {
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/* Software may write all ones to INDEX to determine the
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maximum value supported. */
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env->CP0_MAARI = MIPS_MAAR_MAX - 1;
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} else if (index < MIPS_MAAR_MAX) {
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env->CP0_MAARI = index;
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}
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/* Other than the all ones, if the
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value written is not supported, then INDEX is unchanged
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from its previous value. */
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}
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void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
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void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
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{
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{
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/* Watch exceptions for instructions, data loads, data stores
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/* Watch exceptions for instructions, data loads, data stores
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@ -1433,6 +1433,7 @@ typedef struct DisasContext {
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bool ps;
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bool ps;
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bool vp;
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bool vp;
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bool cmgcr;
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bool cmgcr;
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bool mrp;
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} DisasContext;
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} DisasContext;
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enum {
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enum {
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@ -4816,6 +4817,11 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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ctx->CP0_LLAddr_shift);
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ctx->CP0_LLAddr_shift);
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rn = "LLAddr";
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rn = "LLAddr";
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break;
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break;
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case 1:
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CP0_CHECK(ctx->mrp);
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gen_helper_mfhc0_maar(arg, cpu_env);
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rn = "MAAR";
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break;
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default:
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default:
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goto cp0_unimplemented;
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goto cp0_unimplemented;
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}
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}
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@ -4885,6 +4891,11 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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treating MTHC0 to LLAddr as NOP. */
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treating MTHC0 to LLAddr as NOP. */
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rn = "LLAddr";
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rn = "LLAddr";
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break;
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break;
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case 1:
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CP0_CHECK(ctx->mrp);
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gen_helper_mthc0_maar(cpu_env, arg);
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rn = "MAAR";
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break;
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default:
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default:
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goto cp0_unimplemented;
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goto cp0_unimplemented;
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}
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}
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@ -5351,6 +5362,16 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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gen_helper_mfc0_lladdr(arg, cpu_env);
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gen_helper_mfc0_lladdr(arg, cpu_env);
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rn = "LLAddr";
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rn = "LLAddr";
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break;
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break;
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case 1:
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CP0_CHECK(ctx->mrp);
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gen_helper_mfc0_maar(arg, cpu_env);
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rn = "MAAR";
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break;
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case 2:
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CP0_CHECK(ctx->mrp);
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gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MAARI));
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rn = "MAARI";
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break;
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default:
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default:
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goto cp0_unimplemented;
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goto cp0_unimplemented;
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}
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}
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@ -5996,6 +6017,16 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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gen_helper_mtc0_lladdr(cpu_env, arg);
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gen_helper_mtc0_lladdr(cpu_env, arg);
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rn = "LLAddr";
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rn = "LLAddr";
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break;
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break;
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case 1:
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CP0_CHECK(ctx->mrp);
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gen_helper_mtc0_maar(cpu_env, arg);
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rn = "MAAR";
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break;
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case 2:
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CP0_CHECK(ctx->mrp);
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gen_helper_mtc0_maari(cpu_env, arg);
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rn = "MAARI";
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break;
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default:
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default:
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goto cp0_unimplemented;
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goto cp0_unimplemented;
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}
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}
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@ -6644,6 +6675,16 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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gen_helper_dmfc0_lladdr(arg, cpu_env);
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gen_helper_dmfc0_lladdr(arg, cpu_env);
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rn = "LLAddr";
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rn = "LLAddr";
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break;
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break;
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case 1:
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CP0_CHECK(ctx->mrp);
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gen_helper_dmfc0_maar(arg, cpu_env);
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rn = "MAAR";
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break;
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case 2:
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CP0_CHECK(ctx->mrp);
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gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MAARI));
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rn = "MAARI";
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break;
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default:
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default:
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goto cp0_unimplemented;
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goto cp0_unimplemented;
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}
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}
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@ -7281,6 +7322,16 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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gen_helper_mtc0_lladdr(cpu_env, arg);
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gen_helper_mtc0_lladdr(cpu_env, arg);
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rn = "LLAddr";
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rn = "LLAddr";
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break;
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break;
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case 1:
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CP0_CHECK(ctx->mrp);
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gen_helper_mtc0_maar(cpu_env, arg);
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rn = "MAAR";
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break;
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case 2:
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CP0_CHECK(ctx->mrp);
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gen_helper_mtc0_maari(cpu_env, arg);
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rn = "MAARI";
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break;
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default:
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default:
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goto cp0_unimplemented;
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goto cp0_unimplemented;
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}
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}
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@ -19723,6 +19774,7 @@ void gen_intermediate_code(CPUMIPSState *env, struct TranslationBlock *tb)
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ctx.ps = ((env->active_fpu.fcr0 >> FCR0_PS) & 1) ||
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ctx.ps = ((env->active_fpu.fcr0 >> FCR0_PS) & 1) ||
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(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F));
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(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F));
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ctx.vp = (env->CP0_Config5 >> CP0C5_VP) & 1;
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ctx.vp = (env->CP0_Config5 >> CP0C5_VP) & 1;
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ctx.mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1;
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restore_cpu_state(env, &ctx);
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restore_cpu_state(env, &ctx);
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#ifdef CONFIG_USER_ONLY
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#ifdef CONFIG_USER_ONLY
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ctx.mem_idx = MIPS_HFLAG_UM;
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ctx.mem_idx = MIPS_HFLAG_UM;
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@ -411,7 +411,8 @@ static const mips_def_t mips_defs[] =
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.CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) |
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.CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) |
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(0x1c << CP0C4_KScrExist),
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(0x1c << CP0C4_KScrExist),
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.CP0_Config4_rw_bitmask = 0,
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.CP0_Config4_rw_bitmask = 0,
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.CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_MVH) | (1 << CP0C5_LLB),
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.CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_MVH) | (1 << CP0C5_LLB) |
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(1 << CP0C5_MRP),
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.CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) |
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.CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) |
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(1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) |
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(1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) |
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(1 << CP0C5_FRE) | (1 << CP0C5_UFR),
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(1 << CP0C5_FRE) | (1 << CP0C5_UFR),
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