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hw/arm/smmu: Use enum for SMMU stage

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Currently, translation stage is represented as an int, where 1 is stage-1 and
2 is stage-2, when nested is added, 3 would be confusing to represent nesting,
so we use an enum instead.

While keeping the same values, this is useful for:
 - Doing tricks with bit masks, where BIT(0) is stage-1 and BIT(1) is
   stage-2 and both is nested.
 - Tracing, as stage is printed as int.

Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Mostafa Saleh <smostafa@google.com>
Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20240715084519.1189624-5-smostafa@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Mostafa Saleh 2024-07-15 08:45:04 +00:00 committed by Peter Maydell
parent 2731ea049d
commit f6cc198050
3 changed files with 25 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
hw/arm/smmu-common.c
View File

@ -304,7 +304,7 @@ static int smmu_ptw_64_s1(SMMUTransCfg *cfg,
SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info) SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info)
{ {
dma_addr_t baseaddr, indexmask; dma_addr_t baseaddr, indexmask;
int stage = cfg->stage; SMMUStage stage = cfg->stage;
SMMUTransTableInfo *tt = select_tt(cfg, iova); SMMUTransTableInfo *tt = select_tt(cfg, iova);
uint8_t level, granule_sz, inputsize, stride; uint8_t level, granule_sz, inputsize, stride;
@ -402,7 +402,7 @@ static int smmu_ptw_64_s1(SMMUTransCfg *cfg,
info->type = SMMU_PTW_ERR_TRANSLATION; info->type = SMMU_PTW_ERR_TRANSLATION;
error: error:
info->stage = 1; info->stage = SMMU_STAGE_1;
tlbe->entry.perm = IOMMU_NONE; tlbe->entry.perm = IOMMU_NONE;
return -EINVAL; return -EINVAL;
} }
@ -425,7 +425,7 @@ static int smmu_ptw_64_s2(SMMUTransCfg *cfg,
dma_addr_t ipa, IOMMUAccessFlags perm, dma_addr_t ipa, IOMMUAccessFlags perm,
SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info) SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info)
{ {
const int stage = 2; const SMMUStage stage = SMMU_STAGE_2;
int granule_sz = cfg->s2cfg.granule_sz; int granule_sz = cfg->s2cfg.granule_sz;
/* ARM DDI0487I.a: Table D8-7. */ /* ARM DDI0487I.a: Table D8-7. */
int inputsize = 64 - cfg->s2cfg.tsz; int inputsize = 64 - cfg->s2cfg.tsz;
@ -525,7 +525,7 @@ static int smmu_ptw_64_s2(SMMUTransCfg *cfg,
error_ipa: error_ipa:
info->addr = ipa; info->addr = ipa;
error: error:
info->stage = 2; info->stage = SMMU_STAGE_2;
tlbe->entry.perm = IOMMU_NONE; tlbe->entry.perm = IOMMU_NONE;
return -EINVAL; return -EINVAL;
} }
@ -544,9 +544,9 @@ error:
int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm, int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm,
SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info) SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info)
{ {
if (cfg->stage == 1) { if (cfg->stage == SMMU_STAGE_1) {
return smmu_ptw_64_s1(cfg, iova, perm, tlbe, info); return smmu_ptw_64_s1(cfg, iova, perm, tlbe, info);
} else if (cfg->stage == 2) { } else if (cfg->stage == SMMU_STAGE_2) {
/* /*
* If bypassing stage 1(or unimplemented), the input address is passed * If bypassing stage 1(or unimplemented), the input address is passed
* directly to stage 2 as IPA. If the input address of a transaction * directly to stage 2 as IPA. If the input address of a transaction
@ -555,7 +555,7 @@ int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm,
*/ */
if (iova >= (1ULL << cfg->oas)) { if (iova >= (1ULL << cfg->oas)) {
info->type = SMMU_PTW_ERR_ADDR_SIZE; info->type = SMMU_PTW_ERR_ADDR_SIZE;
info->stage = 1; info->stage = SMMU_STAGE_1;
tlbe->entry.perm = IOMMU_NONE; tlbe->entry.perm = IOMMU_NONE;
return -EINVAL; return -EINVAL;
} }

17
hw/arm/smmuv3.c
View File

@ -34,7 +34,8 @@
#include "smmuv3-internal.h" #include "smmuv3-internal.h"
#include "smmu-internal.h" #include "smmu-internal.h"
#define PTW_RECORD_FAULT(cfg) (((cfg)->stage == 1) ? (cfg)->record_faults : \ #define PTW_RECORD_FAULT(cfg) (((cfg)->stage == SMMU_STAGE_1) ? \
(cfg)->record_faults : \
(cfg)->s2cfg.record_faults) (cfg)->s2cfg.record_faults)
/** /**
@ -402,7 +403,7 @@ static bool s2_pgtable_config_valid(uint8_t sl0, uint8_t t0sz, uint8_t gran)
static int decode_ste_s2_cfg(SMMUTransCfg *cfg, STE *ste) static int decode_ste_s2_cfg(SMMUTransCfg *cfg, STE *ste)
{ {
cfg->stage = 2; cfg->stage = SMMU_STAGE_2;
if (STE_S2AA64(ste) == 0x0) { if (STE_S2AA64(ste) == 0x0) {
qemu_log_mask(LOG_UNIMP, qemu_log_mask(LOG_UNIMP,
@ -678,7 +679,7 @@ static int decode_cd(SMMUTransCfg *cfg, CD *cd, SMMUEventInfo *event)
/* we support only those at the moment */ /* we support only those at the moment */
cfg->aa64 = true; cfg->aa64 = true;
cfg->stage = 1; cfg->stage = SMMU_STAGE_1;
cfg->oas = oas2bits(CD_IPS(cd)); cfg->oas = oas2bits(CD_IPS(cd));
cfg->oas = MIN(oas2bits(SMMU_IDR5_OAS), cfg->oas); cfg->oas = MIN(oas2bits(SMMU_IDR5_OAS), cfg->oas);
@ -762,7 +763,7 @@ static int smmuv3_decode_config(IOMMUMemoryRegion *mr, SMMUTransCfg *cfg,
return ret; return ret;
} }
if (cfg->aborted || cfg->bypassed || (cfg->stage == 2)) { if (cfg->aborted || cfg->bypassed || (cfg->stage == SMMU_STAGE_2)) {
return 0; return 0;
} }
@ -882,7 +883,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
goto epilogue; goto epilogue;
} }
if (cfg->stage == 1) { if (cfg->stage == SMMU_STAGE_1) {
/* Select stage1 translation table. */ /* Select stage1 translation table. */
tt = select_tt(cfg, addr); tt = select_tt(cfg, addr);
if (!tt) { if (!tt) {
@ -919,7 +920,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
* nesting is not supported. So it is sufficient to check the * nesting is not supported. So it is sufficient to check the
* translation stage to know the TLB stage for now. * translation stage to know the TLB stage for now.
*/ */
event.u.f_walk_eabt.s2 = (cfg->stage == 2); event.u.f_walk_eabt.s2 = (cfg->stage == SMMU_STAGE_2);
if (PTW_RECORD_FAULT(cfg)) { if (PTW_RECORD_FAULT(cfg)) {
event.type = SMMU_EVT_F_PERMISSION; event.type = SMMU_EVT_F_PERMISSION;
event.u.f_permission.addr = addr; event.u.f_permission.addr = addr;
@ -935,7 +936,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
if (smmu_ptw(cfg, aligned_addr, flag, cached_entry, &ptw_info)) { if (smmu_ptw(cfg, aligned_addr, flag, cached_entry, &ptw_info)) {
/* All faults from PTW has S2 field. */ /* All faults from PTW has S2 field. */
event.u.f_walk_eabt.s2 = (ptw_info.stage == 2); event.u.f_walk_eabt.s2 = (ptw_info.stage == SMMU_STAGE_2);
g_free(cached_entry); g_free(cached_entry);
switch (ptw_info.type) { switch (ptw_info.type) {
case SMMU_PTW_ERR_WALK_EABT: case SMMU_PTW_ERR_WALK_EABT:
@ -943,7 +944,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
event.u.f_walk_eabt.addr = addr; event.u.f_walk_eabt.addr = addr;
event.u.f_walk_eabt.rnw = flag & 0x1; event.u.f_walk_eabt.rnw = flag & 0x1;
/* Stage-2 (only) is class IN while stage-1 is class TT */ /* Stage-2 (only) is class IN while stage-1 is class TT */
event.u.f_walk_eabt.class = (ptw_info.stage == 2) ? event.u.f_walk_eabt.class = (ptw_info.stage == SMMU_STAGE_2) ?
SMMU_CLASS_IN : SMMU_CLASS_TT; SMMU_CLASS_IN : SMMU_CLASS_TT;
event.u.f_walk_eabt.addr2 = ptw_info.addr; event.u.f_walk_eabt.addr2 = ptw_info.addr;
break; break;

11
include/hw/arm/smmu-common.h
View File

@ -49,8 +49,15 @@ typedef enum {
SMMU_PTW_ERR_PERMISSION, /* Permission fault */ SMMU_PTW_ERR_PERMISSION, /* Permission fault */
} SMMUPTWEventType; } SMMUPTWEventType;
/* SMMU Stage */
typedef enum {
SMMU_STAGE_1 = 1,
SMMU_STAGE_2,
SMMU_NESTED,
} SMMUStage;
typedef struct SMMUPTWEventInfo { typedef struct SMMUPTWEventInfo {
int stage; SMMUStage stage;
SMMUPTWEventType type; SMMUPTWEventType type;
dma_addr_t addr; /* fetched address that induced an abort, if any */ dma_addr_t addr; /* fetched address that induced an abort, if any */
} SMMUPTWEventInfo; } SMMUPTWEventInfo;
@ -88,7 +95,7 @@ typedef struct SMMUS2Cfg {
*/ */
typedef struct SMMUTransCfg { typedef struct SMMUTransCfg {
/* Shared fields between stage-1 and stage-2. */ /* Shared fields between stage-1 and stage-2. */
int stage; /* translation stage */ SMMUStage stage; /* translation stage */
bool disabled; /* smmu is disabled */ bool disabled; /* smmu is disabled */
bool bypassed; /* translation is bypassed */ bool bypassed; /* translation is bypassed */
bool aborted; /* translation is aborted */ bool aborted; /* translation is aborted */