target/arm: Convert SQRDMLAH, SQRDMLSH to decodetree
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240625183536.1672454-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
7619129f0d
commit
f698e45270
@ -979,6 +979,16 @@ DEF_HELPER_FLAGS_5(neon_sqrdmulh_idx_h, TCG_CALL_NO_RWG,
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DEF_HELPER_FLAGS_5(neon_sqrdmulh_idx_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(neon_sqrdmlah_idx_h, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(neon_sqrdmlah_idx_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(neon_sqrdmlsh_idx_h, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(neon_sqrdmlsh_idx_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve2_sqdmulh_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve2_sqdmulh_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve2_sqdmulh_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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@ -781,6 +781,8 @@ CMEQ_s 0111 1110 111 ..... 10001 1 ..... ..... @rrr_d
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SQDMULH_s 0101 1110 ..1 ..... 10110 1 ..... ..... @rrr_e
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SQRDMULH_s 0111 1110 ..1 ..... 10110 1 ..... ..... @rrr_e
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SQRDMLAH_s 0111 1110 ..0 ..... 10000 1 ..... ..... @rrr_e
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SQRDMLSH_s 0111 1110 ..0 ..... 10001 1 ..... ..... @rrr_e
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### Advanced SIMD scalar pairwise
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@ -941,6 +943,8 @@ MLS_v 0.10 1110 ..1 ..... 10010 1 ..... ..... @qrrr_e
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SQDMULH_v 0.00 1110 ..1 ..... 10110 1 ..... ..... @qrrr_e
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SQRDMULH_v 0.10 1110 ..1 ..... 10110 1 ..... ..... @qrrr_e
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SQRDMLAH_v 0.10 1110 ..0 ..... 10000 1 ..... ..... @qrrr_e
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SQRDMLSH_v 0.10 1110 ..0 ..... 10001 1 ..... ..... @qrrr_e
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### Advanced SIMD scalar x indexed element
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@ -966,6 +970,12 @@ SQDMULH_si 0101 1111 10 .. .... 1100 . 0 ..... ..... @rrx_s
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SQRDMULH_si 0101 1111 01 .. .... 1101 . 0 ..... ..... @rrx_h
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SQRDMULH_si 0101 1111 10 . ..... 1101 . 0 ..... ..... @rrx_s
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SQRDMLAH_si 0111 1111 01 .. .... 1101 . 0 ..... ..... @rrx_h
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SQRDMLAH_si 0111 1111 10 .. .... 1101 . 0 ..... ..... @rrx_s
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SQRDMLSH_si 0111 1111 01 .. .... 1111 . 0 ..... ..... @rrx_h
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SQRDMLSH_si 0111 1111 10 .. .... 1111 . 0 ..... ..... @rrx_s
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### Advanced SIMD vector x indexed element
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FMUL_vi 0.00 1111 00 .. .... 1001 . 0 ..... ..... @qrrx_h
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@ -1004,6 +1014,12 @@ SQDMULH_vi 0.00 1111 10 . ..... 1100 . 0 ..... ..... @qrrx_s
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SQRDMULH_vi 0.00 1111 01 .. .... 1101 . 0 ..... ..... @qrrx_h
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SQRDMULH_vi 0.00 1111 10 . ..... 1101 . 0 ..... ..... @qrrx_s
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SQRDMLAH_vi 0.10 1111 01 .. .... 1101 . 0 ..... ..... @qrrx_h
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SQRDMLAH_vi 0.10 1111 10 .. .... 1101 . 0 ..... ..... @qrrx_s
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SQRDMLSH_vi 0.10 1111 01 .. .... 1111 . 0 ..... ..... @qrrx_h
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SQRDMLSH_vi 0.10 1111 10 .. .... 1111 . 0 ..... ..... @qrrx_s
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# Floating-point conditional select
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FCSEL 0001 1110 .. 1 rm:5 cond:4 11 rn:5 rd:5 esz=%esz_hsd
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@ -5235,6 +5235,43 @@ static const ENVScalar2 f_scalar_sqrdmulh = {
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};
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TRANS(SQRDMULH_s, do_env_scalar2_hs, a, &f_scalar_sqrdmulh)
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typedef struct ENVScalar3 {
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NeonGenThreeOpEnvFn *gen_hs[2];
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} ENVScalar3;
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static bool do_env_scalar3_hs(DisasContext *s, arg_rrr_e *a,
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const ENVScalar3 *f)
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{
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TCGv_i32 t0, t1, t2;
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if (a->esz != MO_16 && a->esz != MO_32) {
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return false;
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}
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if (!fp_access_check(s)) {
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return true;
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}
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t0 = tcg_temp_new_i32();
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t1 = tcg_temp_new_i32();
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t2 = tcg_temp_new_i32();
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read_vec_element_i32(s, t0, a->rn, 0, a->esz);
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read_vec_element_i32(s, t1, a->rm, 0, a->esz);
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read_vec_element_i32(s, t2, a->rd, 0, a->esz);
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f->gen_hs[a->esz - 1](t0, tcg_env, t0, t1, t2);
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write_fp_sreg(s, a->rd, t0);
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return true;
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}
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static const ENVScalar3 f_scalar_sqrdmlah = {
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{ gen_helper_neon_qrdmlah_s16, gen_helper_neon_qrdmlah_s32 }
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};
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TRANS_FEAT(SQRDMLAH_s, aa64_rdm, do_env_scalar3_hs, a, &f_scalar_sqrdmlah)
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static const ENVScalar3 f_scalar_sqrdmlsh = {
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{ gen_helper_neon_qrdmlsh_s16, gen_helper_neon_qrdmlsh_s32 }
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};
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TRANS_FEAT(SQRDMLSH_s, aa64_rdm, do_env_scalar3_hs, a, &f_scalar_sqrdmlsh)
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static bool do_cmop_d(DisasContext *s, arg_rrr_e *a, TCGCond cond)
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{
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if (fp_access_check(s)) {
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@ -5552,6 +5589,8 @@ TRANS(CMTST_v, do_gvec_fn3, a, gen_gvec_cmtst)
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TRANS(SQDMULH_v, do_gvec_fn3_no8_no64, a, gen_gvec_sqdmulh_qc)
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TRANS(SQRDMULH_v, do_gvec_fn3_no8_no64, a, gen_gvec_sqrdmulh_qc)
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TRANS_FEAT(SQRDMLAH_v, aa64_rdm, do_gvec_fn3_no8_no64, a, gen_gvec_sqrdmlah_qc)
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TRANS_FEAT(SQRDMLSH_v, aa64_rdm, do_gvec_fn3_no8_no64, a, gen_gvec_sqrdmlsh_qc)
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/*
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* Advanced SIMD scalar/vector x indexed element
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@ -5681,6 +5720,29 @@ static bool do_env_scalar2_idx_hs(DisasContext *s, arg_rrx_e *a,
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TRANS(SQDMULH_si, do_env_scalar2_idx_hs, a, &f_scalar_sqdmulh)
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TRANS(SQRDMULH_si, do_env_scalar2_idx_hs, a, &f_scalar_sqrdmulh)
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static bool do_env_scalar3_idx_hs(DisasContext *s, arg_rrx_e *a,
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const ENVScalar3 *f)
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{
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if (a->esz < MO_16 || a->esz > MO_32) {
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return false;
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}
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if (fp_access_check(s)) {
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TCGv_i32 t0 = tcg_temp_new_i32();
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TCGv_i32 t1 = tcg_temp_new_i32();
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TCGv_i32 t2 = tcg_temp_new_i32();
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read_vec_element_i32(s, t0, a->rn, 0, a->esz);
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read_vec_element_i32(s, t1, a->rm, a->idx, a->esz);
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read_vec_element_i32(s, t2, a->rd, 0, a->esz);
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f->gen_hs[a->esz - 1](t0, tcg_env, t0, t1, t2);
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write_fp_sreg(s, a->rd, t0);
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}
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return true;
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}
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TRANS_FEAT(SQRDMLAH_si, aa64_rdm, do_env_scalar3_idx_hs, a, &f_scalar_sqrdmlah)
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TRANS_FEAT(SQRDMLSH_si, aa64_rdm, do_env_scalar3_idx_hs, a, &f_scalar_sqrdmlsh)
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static bool do_fp3_vector_idx(DisasContext *s, arg_qrrx_e *a,
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gen_helper_gvec_3_ptr * const fns[3])
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{
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@ -5838,6 +5900,20 @@ static gen_helper_gvec_4 * const f_vector_idx_sqrdmulh[2] = {
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};
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TRANS(SQRDMULH_vi, do_int3_qc_vector_idx, a, f_vector_idx_sqrdmulh)
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static gen_helper_gvec_4 * const f_vector_idx_sqrdmlah[2] = {
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gen_helper_neon_sqrdmlah_idx_h,
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gen_helper_neon_sqrdmlah_idx_s,
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};
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TRANS_FEAT(SQRDMLAH_vi, aa64_rdm, do_int3_qc_vector_idx, a,
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f_vector_idx_sqrdmlah)
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static gen_helper_gvec_4 * const f_vector_idx_sqrdmlsh[2] = {
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gen_helper_neon_sqrdmlsh_idx_h,
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gen_helper_neon_sqrdmlsh_idx_s,
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};
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TRANS_FEAT(SQRDMLSH_vi, aa64_rdm, do_int3_qc_vector_idx, a,
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f_vector_idx_sqrdmlsh)
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/*
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* Advanced SIMD scalar pairwise
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*/
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@ -9536,84 +9612,6 @@ static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn)
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}
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}
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/* AdvSIMD scalar three same extra
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* 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
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* +-----+---+-----------+------+---+------+---+--------+---+----+----+
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* | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
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* +-----+---+-----------+------+---+------+---+--------+---+----+----+
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*/
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static void disas_simd_scalar_three_reg_same_extra(DisasContext *s,
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uint32_t insn)
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{
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int rd = extract32(insn, 0, 5);
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int rn = extract32(insn, 5, 5);
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int opcode = extract32(insn, 11, 4);
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int rm = extract32(insn, 16, 5);
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int size = extract32(insn, 22, 2);
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bool u = extract32(insn, 29, 1);
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TCGv_i32 ele1, ele2, ele3;
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TCGv_i64 res;
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bool feature;
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switch (u * 16 + opcode) {
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case 0x10: /* SQRDMLAH (vector) */
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case 0x11: /* SQRDMLSH (vector) */
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if (size != 1 && size != 2) {
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unallocated_encoding(s);
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return;
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}
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feature = dc_isar_feature(aa64_rdm, s);
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break;
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default:
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unallocated_encoding(s);
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return;
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}
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if (!feature) {
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unallocated_encoding(s);
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return;
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}
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if (!fp_access_check(s)) {
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return;
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}
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/* Do a single operation on the lowest element in the vector.
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* We use the standard Neon helpers and rely on 0 OP 0 == 0
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* with no side effects for all these operations.
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* OPTME: special-purpose helpers would avoid doing some
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* unnecessary work in the helper for the 16 bit cases.
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*/
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ele1 = tcg_temp_new_i32();
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ele2 = tcg_temp_new_i32();
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ele3 = tcg_temp_new_i32();
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read_vec_element_i32(s, ele1, rn, 0, size);
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read_vec_element_i32(s, ele2, rm, 0, size);
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read_vec_element_i32(s, ele3, rd, 0, size);
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switch (opcode) {
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case 0x0: /* SQRDMLAH */
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if (size == 1) {
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gen_helper_neon_qrdmlah_s16(ele3, tcg_env, ele1, ele2, ele3);
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} else {
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gen_helper_neon_qrdmlah_s32(ele3, tcg_env, ele1, ele2, ele3);
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}
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break;
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case 0x1: /* SQRDMLSH */
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if (size == 1) {
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gen_helper_neon_qrdmlsh_s16(ele3, tcg_env, ele1, ele2, ele3);
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} else {
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gen_helper_neon_qrdmlsh_s32(ele3, tcg_env, ele1, ele2, ele3);
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}
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break;
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default:
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g_assert_not_reached();
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}
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res = tcg_temp_new_i64();
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tcg_gen_extu_i32_i64(res, ele3);
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write_fp_dreg(s, rd, res);
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}
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static void handle_2misc_64(DisasContext *s, int opcode, bool u,
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TCGv_i64 tcg_rd, TCGv_i64 tcg_rn,
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TCGv_i32 tcg_rmode, TCGv_ptr tcg_fpstatus)
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@ -10892,14 +10890,6 @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
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int rot;
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switch (u * 16 + opcode) {
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case 0x10: /* SQRDMLAH (vector) */
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case 0x11: /* SQRDMLSH (vector) */
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if (size != 1 && size != 2) {
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unallocated_encoding(s);
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return;
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}
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feature = dc_isar_feature(aa64_rdm, s);
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break;
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case 0x02: /* SDOT (vector) */
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case 0x12: /* UDOT (vector) */
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if (size != MO_32) {
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@ -10957,6 +10947,8 @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
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}
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break;
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default:
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case 0x10: /* SQRDMLAH (vector) */
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case 0x11: /* SQRDMLSH (vector) */
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unallocated_encoding(s);
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return;
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}
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@ -10969,14 +10961,6 @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
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}
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switch (opcode) {
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case 0x0: /* SQRDMLAH (vector) */
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gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_sqrdmlah_qc, size);
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return;
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case 0x1: /* SQRDMLSH (vector) */
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gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_sqrdmlsh_qc, size);
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return;
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case 0x2: /* SDOT / UDOT */
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gen_gvec_op4_ool(s, is_q, rd, rn, rm, rd, 0,
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u ? gen_helper_gvec_udot_b : gen_helper_gvec_sdot_b);
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@ -12059,13 +12043,6 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
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case 0x0b: /* SQDMULL, SQDMULL2 */
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is_long = true;
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break;
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case 0x1d: /* SQRDMLAH */
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case 0x1f: /* SQRDMLSH */
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if (!dc_isar_feature(aa64_rdm, s)) {
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unallocated_encoding(s);
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return;
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}
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break;
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case 0x0e: /* SDOT */
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case 0x1e: /* UDOT */
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if (is_scalar || size != MO_32 || !dc_isar_feature(aa64_dp, s)) {
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@ -12127,6 +12104,8 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
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case 0x18: /* FMLAL2 */
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case 0x19: /* FMULX */
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case 0x1c: /* FMLSL2 */
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case 0x1d: /* SQRDMLAH */
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case 0x1f: /* SQRDMLSH */
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unallocated_encoding(s);
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return;
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}
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@ -12320,33 +12299,13 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
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tcg_op, tcg_idx);
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}
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break;
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case 0x1d: /* SQRDMLAH */
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read_vec_element_i32(s, tcg_res, rd, pass,
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is_scalar ? size : MO_32);
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if (size == 1) {
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gen_helper_neon_qrdmlah_s16(tcg_res, tcg_env,
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tcg_op, tcg_idx, tcg_res);
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} else {
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gen_helper_neon_qrdmlah_s32(tcg_res, tcg_env,
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tcg_op, tcg_idx, tcg_res);
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}
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break;
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case 0x1f: /* SQRDMLSH */
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read_vec_element_i32(s, tcg_res, rd, pass,
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is_scalar ? size : MO_32);
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if (size == 1) {
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gen_helper_neon_qrdmlsh_s16(tcg_res, tcg_env,
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tcg_op, tcg_idx, tcg_res);
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} else {
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gen_helper_neon_qrdmlsh_s32(tcg_res, tcg_env,
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tcg_op, tcg_idx, tcg_res);
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}
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break;
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default:
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case 0x01: /* FMLA */
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case 0x05: /* FMLS */
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case 0x09: /* FMUL */
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case 0x19: /* FMULX */
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case 0x1d: /* SQRDMLAH */
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case 0x1f: /* SQRDMLSH */
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g_assert_not_reached();
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}
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@ -12538,7 +12497,6 @@ static const AArch64DecodeTable data_proc_simd[] = {
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{ 0x0e000000, 0xbf208c00, disas_simd_tb },
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{ 0x0e000800, 0xbf208c00, disas_simd_zip_trn },
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{ 0x2e000000, 0xbf208400, disas_simd_ext },
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{ 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra },
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{ 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff },
|
||||
{ 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc },
|
||||
{ 0x5f000000, 0xdf000400, disas_simd_indexed }, /* scalar indexed */
|
||||
|
||||
@ -347,6 +347,42 @@ void HELPER(neon_sqrdmulh_idx_h)(void *vd, void *vn, void *vm,
|
||||
clear_tail(d, opr_sz, simd_maxsz(desc));
|
||||
}
|
||||
|
||||
void HELPER(neon_sqrdmlah_idx_h)(void *vd, void *vn, void *vm,
|
||||
void *vq, uint32_t desc)
|
||||
{
|
||||
intptr_t i, j, opr_sz = simd_oprsz(desc);
|
||||
int idx = simd_data(desc);
|
||||
int16_t *d = vd, *n = vn, *m = (int16_t *)vm + H2(idx);
|
||||
intptr_t elements = opr_sz / 2;
|
||||
intptr_t eltspersegment = MIN(16 / 2, elements);
|
||||
|
||||
for (i = 0; i < elements; i += 16 / 2) {
|
||||
int16_t mm = m[i];
|
||||
for (j = 0; j < eltspersegment; ++j) {
|
||||
d[i + j] = do_sqrdmlah_h(n[i + j], mm, d[i + j], false, true, vq);
|
||||
}
|
||||
}
|
||||
clear_tail(d, opr_sz, simd_maxsz(desc));
|
||||
}
|
||||
|
||||
void HELPER(neon_sqrdmlsh_idx_h)(void *vd, void *vn, void *vm,
|
||||
void *vq, uint32_t desc)
|
||||
{
|
||||
intptr_t i, j, opr_sz = simd_oprsz(desc);
|
||||
int idx = simd_data(desc);
|
||||
int16_t *d = vd, *n = vn, *m = (int16_t *)vm + H2(idx);
|
||||
intptr_t elements = opr_sz / 2;
|
||||
intptr_t eltspersegment = MIN(16 / 2, elements);
|
||||
|
||||
for (i = 0; i < elements; i += 16 / 2) {
|
||||
int16_t mm = m[i];
|
||||
for (j = 0; j < eltspersegment; ++j) {
|
||||
d[i + j] = do_sqrdmlah_h(n[i + j], mm, d[i + j], true, true, vq);
|
||||
}
|
||||
}
|
||||
clear_tail(d, opr_sz, simd_maxsz(desc));
|
||||
}
|
||||
|
||||
void HELPER(sve2_sqrdmlah_h)(void *vd, void *vn, void *vm,
|
||||
void *va, uint32_t desc)
|
||||
{
|
||||
@ -546,6 +582,42 @@ void HELPER(neon_sqrdmulh_idx_s)(void *vd, void *vn, void *vm,
|
||||
clear_tail(d, opr_sz, simd_maxsz(desc));
|
||||
}
|
||||
|
||||
void HELPER(neon_sqrdmlah_idx_s)(void *vd, void *vn, void *vm,
|
||||
void *vq, uint32_t desc)
|
||||
{
|
||||
intptr_t i, j, opr_sz = simd_oprsz(desc);
|
||||
int idx = simd_data(desc);
|
||||
int32_t *d = vd, *n = vn, *m = (int32_t *)vm + H4(idx);
|
||||
intptr_t elements = opr_sz / 4;
|
||||
intptr_t eltspersegment = MIN(16 / 4, elements);
|
||||
|
||||
for (i = 0; i < elements; i += 16 / 4) {
|
||||
int32_t mm = m[i];
|
||||
for (j = 0; j < eltspersegment; ++j) {
|
||||
d[i + j] = do_sqrdmlah_s(n[i + j], mm, d[i + j], false, true, vq);
|
||||
}
|
||||
}
|
||||
clear_tail(d, opr_sz, simd_maxsz(desc));
|
||||
}
|
||||
|
||||
void HELPER(neon_sqrdmlsh_idx_s)(void *vd, void *vn, void *vm,
|
||||
void *vq, uint32_t desc)
|
||||
{
|
||||
intptr_t i, j, opr_sz = simd_oprsz(desc);
|
||||
int idx = simd_data(desc);
|
||||
int32_t *d = vd, *n = vn, *m = (int32_t *)vm + H4(idx);
|
||||
intptr_t elements = opr_sz / 4;
|
||||
intptr_t eltspersegment = MIN(16 / 4, elements);
|
||||
|
||||
for (i = 0; i < elements; i += 16 / 4) {
|
||||
int32_t mm = m[i];
|
||||
for (j = 0; j < eltspersegment; ++j) {
|
||||
d[i + j] = do_sqrdmlah_s(n[i + j], mm, d[i + j], true, true, vq);
|
||||
}
|
||||
}
|
||||
clear_tail(d, opr_sz, simd_maxsz(desc));
|
||||
}
|
||||
|
||||
void HELPER(sve2_sqrdmlah_s)(void *vd, void *vn, void *vm,
|
||||
void *va, uint32_t desc)
|
||||
{
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user