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target/arm: Convert VMINNM, VMAXNM to decodetree

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Convert the VMINNM and VMAXNM instructions to decodetree.
As with VSEL, we leave the trans_VMINMAXNM() function
in translate.c for the moment.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Peter Maydell 2019-06-11 16:39:43 +01:00
parent b3ff4b87b4
commit f65988a1ef
2 changed files with 33 additions and 13 deletions
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39
target/arm/translate.c
View File

@ -3202,11 +3202,31 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
return true; return true;
} }
static int handle_vminmaxnm(uint32_t insn, uint32_t rd, uint32_t rn, static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM *a)
uint32_t rm, uint32_t dp)
{ {
uint32_t vmin = extract32(insn, 6, 1); uint32_t rd, rn, rm;
TCGv_ptr fpst = get_fpstatus_ptr(0); bool dp = a->dp;
bool vmin = a->op;
TCGv_ptr fpst;
if (!dc_isar_feature(aa32_vminmaxnm, s)) {
return false;
}
/* UNDEF accesses to D16-D31 if they don't exist */
if (dp && !dc_isar_feature(aa32_fp_d32, s) &&
((a->vm | a->vn | a->vd) & 0x10)) {
return false;
}
rd = a->vd;
rn = a->vn;
rm = a->vm;
if (!vfp_access_check(s)) {
return true;
}
fpst = get_fpstatus_ptr(0);
if (dp) { if (dp) {
TCGv_i64 frn, frm, dest; TCGv_i64 frn, frm, dest;
@ -3247,7 +3267,7 @@ static int handle_vminmaxnm(uint32_t insn, uint32_t rd, uint32_t rn,
} }
tcg_temp_free_ptr(fpst); tcg_temp_free_ptr(fpst);
return 0; return true;
} }
static int handle_vrint(uint32_t insn, uint32_t rd, uint32_t rm, uint32_t dp, static int handle_vrint(uint32_t insn, uint32_t rd, uint32_t rm, uint32_t dp,
@ -3359,22 +3379,17 @@ static const uint8_t fp_decode_rm[] = {
static int disas_vfp_misc_insn(DisasContext *s, uint32_t insn) static int disas_vfp_misc_insn(DisasContext *s, uint32_t insn)
{ {
uint32_t rd, rn, rm, dp = extract32(insn, 8, 1); uint32_t rd, rm, dp = extract32(insn, 8, 1);
if (dp) { if (dp) {
VFP_DREG_D(rd, insn); VFP_DREG_D(rd, insn);
VFP_DREG_N(rn, insn);
VFP_DREG_M(rm, insn); VFP_DREG_M(rm, insn);
} else { } else {
rd = VFP_SREG_D(insn); rd = VFP_SREG_D(insn);
rn = VFP_SREG_N(insn);
rm = VFP_SREG_M(insn); rm = VFP_SREG_M(insn);
} }
if ((insn & 0x0fb00e10) == 0x0e800a00 && if ((insn & 0x0fbc0ed0) == 0x0eb80a40 &&
dc_isar_feature(aa32_vminmaxnm, s)) {
return handle_vminmaxnm(insn, rd, rn, rm, dp);
} else if ((insn & 0x0fbc0ed0) == 0x0eb80a40 &&
dc_isar_feature(aa32_vrint, s)) { dc_isar_feature(aa32_vrint, s)) {
/* VRINTA, VRINTN, VRINTP, VRINTM */ /* VRINTA, VRINTN, VRINTP, VRINTM */
int rounding = fp_decode_rm[extract32(insn, 16, 2)]; int rounding = fp_decode_rm[extract32(insn, 16, 2)];

5
target/arm/vfp-uncond.decode
View File

@ -45,3 +45,8 @@ VSEL 1111 1110 0. cc:2 .... .... 1010 .0.0 .... \
vm=%vm_sp vn=%vn_sp vd=%vd_sp dp=0 vm=%vm_sp vn=%vn_sp vd=%vd_sp dp=0
VSEL 1111 1110 0. cc:2 .... .... 1011 .0.0 .... \ VSEL 1111 1110 0. cc:2 .... .... 1011 .0.0 .... \
vm=%vm_dp vn=%vn_dp vd=%vd_dp dp=1 vm=%vm_dp vn=%vn_dp vd=%vd_dp dp=1
VMINMAXNM 1111 1110 1.00 .... .... 1010 . op:1 .0 .... \
vm=%vm_sp vn=%vn_sp vd=%vd_sp dp=0
VMINMAXNM 1111 1110 1.00 .... .... 1011 . op:1 .0 .... \
vm=%vm_dp vn=%vn_dp vd=%vd_dp dp=1