From f5d9c1089f0136c2aadf51389e93a94d517e430f Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Tue, 7 Jun 2016 12:50:20 +1000 Subject: [PATCH] ppc: Properly tag the translation cache based on MMU mode We used to always flush the TLB when changing relocation mode in MSR:IR and MSR:DR (ie. MMU on/off for Instructions and Data). We don't anymore since we have split mmu_idx for instruction and data. However, since we hard code the mmu_idx in the translated code, we now need to also make sure MSR:IR and MSR:DR are part of the hflags used to tag translated code, so that we use different translated code for different MMU settings. Darwin gets hurt by this problem. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: David Gibson --- target-ppc/helper_regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-ppc/helper_regs.h b/target-ppc/helper_regs.h index 12af61cbf1..104b690093 100644 --- a/target-ppc/helper_regs.h +++ b/target-ppc/helper_regs.h @@ -95,7 +95,7 @@ static inline void hreg_compute_hflags(CPUPPCState *env) /* We 'forget' FE0 & FE1: we'll never generate imprecise exceptions */ hflags_mask = (1 << MSR_VR) | (1 << MSR_AP) | (1 << MSR_SA) | (1 << MSR_PR) | (1 << MSR_FP) | (1 << MSR_SE) | (1 << MSR_BE) | - (1 << MSR_LE) | (1 << MSR_VSX); + (1 << MSR_LE) | (1 << MSR_VSX) | (1 << MSR_IR) | (1 << MSR_DR); hflags_mask |= (1ULL << MSR_CM) | (1ULL << MSR_SF) | MSR_HVB; hreg_compute_mem_idx(env); env->hflags = env->msr & hflags_mask;