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pci: Convert child classes of TYPE_PCIE_ROOT_PORT to 3-phase reset

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Convert the TYPE_CXL_ROOT_PORT and TYPE_PNV_PHB_ROOT_PORT classes to
3-phase reset, so they don't need to use the deprecated
device_class_set_parent_reset() function any more.

We have to do both in the same commit, because they keep the
parent_reset field in their common parent class's class struct.

Note that pnv_phb_root_port_class_init() was pointlessly setting
dc->reset twice, once by calling device_class_set_parent_reset()
and once directly.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20221125115240.3005559-5-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2022-11-25 11:52:37 +00:00
parent bb27210c8c
commit f4c636b0c2
3 changed files with 20 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
hw/pci-bridge/cxl_root_port.c
View File

@ -138,12 +138,14 @@ static void cxl_rp_realize(DeviceState *dev, Error **errp)
component_bar); component_bar);
} }
static void cxl_rp_reset(DeviceState *dev) static void cxl_rp_reset_hold(Object *obj)
{ {
PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev); PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(obj);
CXLRootPort *crp = CXL_ROOT_PORT(dev); CXLRootPort *crp = CXL_ROOT_PORT(obj);
rpc->parent_reset(dev); if (rpc->parent_phases.hold) {
rpc->parent_phases.hold(obj);
}
latch_registers(crp); latch_registers(crp);
} }
@ -199,6 +201,7 @@ static void cxl_root_port_class_init(ObjectClass *oc, void *data)
{ {
DeviceClass *dc = DEVICE_CLASS(oc); DeviceClass *dc = DEVICE_CLASS(oc);
PCIDeviceClass *k = PCI_DEVICE_CLASS(oc); PCIDeviceClass *k = PCI_DEVICE_CLASS(oc);
ResettableClass *rc = RESETTABLE_CLASS(oc);
PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(oc); PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(oc);
k->vendor_id = PCI_VENDOR_ID_INTEL; k->vendor_id = PCI_VENDOR_ID_INTEL;
@ -209,7 +212,8 @@ static void cxl_root_port_class_init(ObjectClass *oc, void *data)
k->config_write = cxl_rp_write_config; k->config_write = cxl_rp_write_config;
device_class_set_parent_realize(dc, cxl_rp_realize, &rpc->parent_realize); device_class_set_parent_realize(dc, cxl_rp_realize, &rpc->parent_realize);
device_class_set_parent_reset(dc, cxl_rp_reset, &rpc->parent_reset); resettable_class_set_parent_phases(rc, NULL, cxl_rp_reset_hold, NULL,
&rpc->parent_phases);
rpc->aer_offset = GEN_PCIE_ROOT_PORT_AER_OFFSET; rpc->aer_offset = GEN_PCIE_ROOT_PORT_AER_OFFSET;
rpc->acs_offset = GEN_PCIE_ROOT_PORT_ACS_OFFSET; rpc->acs_offset = GEN_PCIE_ROOT_PORT_ACS_OFFSET;

18
hw/pci-host/pnv_phb.c
View File

@ -199,14 +199,16 @@ static void pnv_phb_class_init(ObjectClass *klass, void *data)
dc->user_creatable = true; dc->user_creatable = true;
} }
static void pnv_phb_root_port_reset(DeviceState *dev) static void pnv_phb_root_port_reset_hold(Object *obj)
{ {
PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev); PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(obj);
PnvPHBRootPort *phb_rp = PNV_PHB_ROOT_PORT(dev); PnvPHBRootPort *phb_rp = PNV_PHB_ROOT_PORT(obj);
PCIDevice *d = PCI_DEVICE(dev); PCIDevice *d = PCI_DEVICE(obj);
uint8_t *conf = d->config; uint8_t *conf = d->config;
rpc->parent_reset(dev); if (rpc->parent_phases.hold) {
rpc->parent_phases.hold(obj);
}
if (phb_rp->version == 3) { if (phb_rp->version == 3) {
return; return;
@ -300,6 +302,7 @@ static Property pnv_phb_root_port_properties[] = {
static void pnv_phb_root_port_class_init(ObjectClass *klass, void *data) static void pnv_phb_root_port_class_init(ObjectClass *klass, void *data)
{ {
DeviceClass *dc = DEVICE_CLASS(klass); DeviceClass *dc = DEVICE_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass); PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass);
@ -308,9 +311,8 @@ static void pnv_phb_root_port_class_init(ObjectClass *klass, void *data)
device_class_set_props(dc, pnv_phb_root_port_properties); device_class_set_props(dc, pnv_phb_root_port_properties);
device_class_set_parent_realize(dc, pnv_phb_root_port_realize, device_class_set_parent_realize(dc, pnv_phb_root_port_realize,
&rpc->parent_realize); &rpc->parent_realize);
device_class_set_parent_reset(dc, pnv_phb_root_port_reset, resettable_class_set_parent_phases(rc, NULL, pnv_phb_root_port_reset_hold,
&rpc->parent_reset); NULL, &rpc->parent_phases);
dc->reset = &pnv_phb_root_port_reset;
dc->user_creatable = true; dc->user_creatable = true;
k->vendor_id = PCI_VENDOR_ID_IBM; k->vendor_id = PCI_VENDOR_ID_IBM;

2
include/hw/pci/pcie_port.h
View File

@ -80,7 +80,7 @@ DECLARE_CLASS_CHECKERS(PCIERootPortClass, PCIE_ROOT_PORT,
struct PCIERootPortClass { struct PCIERootPortClass {
PCIDeviceClass parent_class; PCIDeviceClass parent_class;
DeviceRealize parent_realize; DeviceRealize parent_realize;
DeviceReset parent_reset; ResettablePhases parent_phases;
uint8_t (*aer_vector)(const PCIDevice *dev); uint8_t (*aer_vector)(const PCIDevice *dev);
int (*interrupts_init)(PCIDevice *dev, Error **errp); int (*interrupts_init)(PCIDevice *dev, Error **errp);