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hw/intc/arm_gicv3: Report the NMI interrupt in gicv3_cpuif_update()

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In CPU Interface, if the IRQ has the non-maskable property, report NMI to
the corresponding PE.

Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-22-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Jinjie Ruan 2024-04-19 14:33:05 +01:00 committed by Peter Maydell
parent d89daa893f
commit f3c26a44fe
1 changed files with 4 additions and 0 deletions
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4
hw/intc/arm_gicv3_cpuif.c
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@ -1038,6 +1038,7 @@ void gicv3_cpuif_update(GICv3CPUState *cs)
/* Tell the CPU about its highest priority pending interrupt */ /* Tell the CPU about its highest priority pending interrupt */
int irqlevel = 0; int irqlevel = 0;
int fiqlevel = 0; int fiqlevel = 0;
int nmilevel = 0;
ARMCPU *cpu = ARM_CPU(cs->cpu); ARMCPU *cpu = ARM_CPU(cs->cpu);
CPUARMState *env = &cpu->env; CPUARMState *env = &cpu->env;
@ -1076,6 +1077,8 @@ void gicv3_cpuif_update(GICv3CPUState *cs)
if (isfiq) { if (isfiq) {
fiqlevel = 1; fiqlevel = 1;
} else if (cs->hppi.nmi) {
nmilevel = 1;
} else { } else {
irqlevel = 1; irqlevel = 1;
} }
@ -1085,6 +1088,7 @@ void gicv3_cpuif_update(GICv3CPUState *cs)
qemu_set_irq(cs->parent_fiq, fiqlevel); qemu_set_irq(cs->parent_fiq, fiqlevel);
qemu_set_irq(cs->parent_irq, irqlevel); qemu_set_irq(cs->parent_irq, irqlevel);
qemu_set_irq(cs->parent_nmi, nmilevel);
} }
static uint64_t icc_pmr_read(CPUARMState *env, const ARMCPRegInfo *ri) static uint64_t icc_pmr_read(CPUARMState *env, const ARMCPRegInfo *ri)