mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

ppc405_uc: Pass PowerPCCPU to ppc40x_{core,chip,system}_reset()

Browse Source 
Prepares for changing cpu_interrupt() argument to CPUState.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Andreas Färber 2013-01-18 15:57:51 +01:00
parent 25733eada6
commit f3273ba643
3 changed files with 19 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
hw/ppc.c
View File

@ -300,20 +300,20 @@ static void ppc40x_set_irq(void *opaque, int pin, int level)
if (level) { if (level) {
LOG_IRQ("%s: reset the PowerPC system\n", LOG_IRQ("%s: reset the PowerPC system\n",
__func__); __func__);
ppc40x_system_reset(env); ppc40x_system_reset(cpu);
} }
break; break;
case PPC40x_INPUT_RESET_CHIP: case PPC40x_INPUT_RESET_CHIP:
if (level) { if (level) {
LOG_IRQ("%s: reset the PowerPC chip\n", __func__); LOG_IRQ("%s: reset the PowerPC chip\n", __func__);
ppc40x_chip_reset(env); ppc40x_chip_reset(cpu);
} }
break; break;
case PPC40x_INPUT_RESET_CORE: case PPC40x_INPUT_RESET_CORE:
/* XXX: TODO: update DBSR[MRR] */ /* XXX: TODO: update DBSR[MRR] */
if (level) { if (level) {
LOG_IRQ("%s: reset the PowerPC core\n", __func__); LOG_IRQ("%s: reset the PowerPC core\n", __func__);
ppc40x_core_reset(env); ppc40x_core_reset(cpu);
} }
break; break;
case PPC40x_INPUT_CINT: case PPC40x_INPUT_CINT:
@ -1011,13 +1011,13 @@ static void cpu_4xx_wdt_cb (void *opaque)
/* No reset */ /* No reset */
break; break;
case 0x1: /* Core reset */ case 0x1: /* Core reset */
ppc40x_core_reset(env); ppc40x_core_reset(cpu);
break; break;
case 0x2: /* Chip reset */ case 0x2: /* Chip reset */
ppc40x_chip_reset(env); ppc40x_chip_reset(cpu);
break; break;
case 0x3: /* System reset */ case 0x3: /* System reset */
ppc40x_system_reset(env); ppc40x_system_reset(cpu);
break; break;
} }
} }

6
hw/ppc.h
View File

@ -58,9 +58,9 @@ clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq,
unsigned int decr_excp); unsigned int decr_excp);
/* Embedded PowerPC reset */ /* Embedded PowerPC reset */
void ppc40x_core_reset (CPUPPCState *env); void ppc40x_core_reset(PowerPCCPU *cpu);
void ppc40x_chip_reset (CPUPPCState *env); void ppc40x_chip_reset(PowerPCCPU *cpu);
void ppc40x_system_reset (CPUPPCState *env); void ppc40x_system_reset(PowerPCCPU *cpu);
void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val); void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
extern CPUWriteMemoryFunc * const PPC_io_write[]; extern CPUWriteMemoryFunc * const PPC_io_write[];

16
hw/ppc405_uc.c
View File

@ -1770,8 +1770,9 @@ static void ppc405_mal_init(CPUPPCState *env, qemu_irq irqs[4])
/*****************************************************************************/ /*****************************************************************************/
/* SPR */ /* SPR */
void ppc40x_core_reset (CPUPPCState *env) void ppc40x_core_reset(PowerPCCPU *cpu)
{ {
CPUPPCState *env = &cpu->env;
target_ulong dbsr; target_ulong dbsr;
printf("Reset PowerPC core\n"); printf("Reset PowerPC core\n");
@ -1782,8 +1783,9 @@ void ppc40x_core_reset (CPUPPCState *env)
env->spr[SPR_40x_DBSR] = dbsr; env->spr[SPR_40x_DBSR] = dbsr;
} }
void ppc40x_chip_reset (CPUPPCState *env) void ppc40x_chip_reset(PowerPCCPU *cpu)
{ {
CPUPPCState *env = &cpu->env;
target_ulong dbsr; target_ulong dbsr;
printf("Reset PowerPC chip\n"); printf("Reset PowerPC chip\n");
@ -1795,7 +1797,7 @@ void ppc40x_chip_reset (CPUPPCState *env)
env->spr[SPR_40x_DBSR] = dbsr; env->spr[SPR_40x_DBSR] = dbsr;
} }
void ppc40x_system_reset (CPUPPCState *env) void ppc40x_system_reset(PowerPCCPU *cpu)
{ {
printf("Reset PowerPC system\n"); printf("Reset PowerPC system\n");
qemu_system_reset_request(); qemu_system_reset_request();
@ -1803,21 +1805,23 @@ void ppc40x_system_reset (CPUPPCState *env)
void store_40x_dbcr0 (CPUPPCState *env, uint32_t val) void store_40x_dbcr0 (CPUPPCState *env, uint32_t val)
{ {
PowerPCCPU *cpu = ppc_env_get_cpu(env);
switch ((val >> 28) & 0x3) { switch ((val >> 28) & 0x3) {
case 0x0: case 0x0:
/* No action */ /* No action */
break; break;
case 0x1: case 0x1:
/* Core reset */ /* Core reset */
ppc40x_core_reset(env); ppc40x_core_reset(cpu);
break; break;
case 0x2: case 0x2:
/* Chip reset */ /* Chip reset */
ppc40x_chip_reset(env); ppc40x_chip_reset(cpu);
break; break;
case 0x3: case 0x3:
/* System reset */ /* System reset */
ppc40x_system_reset(env); ppc40x_system_reset(cpu);
break; break;
} }
} }