ppc405_uc: Pass PowerPCCPU to ppc40x_{core,chip,system}_reset()
Prepares for changing cpu_interrupt() argument to CPUState. Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Alexander Graf <agraf@suse.de>
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25733eada6
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12
hw/ppc.c
12
hw/ppc.c
@ -300,20 +300,20 @@ static void ppc40x_set_irq(void *opaque, int pin, int level)
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if (level) {
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LOG_IRQ("%s: reset the PowerPC system\n",
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__func__);
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ppc40x_system_reset(env);
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ppc40x_system_reset(cpu);
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}
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break;
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case PPC40x_INPUT_RESET_CHIP:
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if (level) {
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LOG_IRQ("%s: reset the PowerPC chip\n", __func__);
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ppc40x_chip_reset(env);
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ppc40x_chip_reset(cpu);
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}
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break;
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case PPC40x_INPUT_RESET_CORE:
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/* XXX: TODO: update DBSR[MRR] */
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if (level) {
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LOG_IRQ("%s: reset the PowerPC core\n", __func__);
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ppc40x_core_reset(env);
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ppc40x_core_reset(cpu);
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}
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break;
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case PPC40x_INPUT_CINT:
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@ -1011,13 +1011,13 @@ static void cpu_4xx_wdt_cb (void *opaque)
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/* No reset */
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break;
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case 0x1: /* Core reset */
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ppc40x_core_reset(env);
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ppc40x_core_reset(cpu);
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break;
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case 0x2: /* Chip reset */
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ppc40x_chip_reset(env);
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ppc40x_chip_reset(cpu);
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break;
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case 0x3: /* System reset */
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ppc40x_system_reset(env);
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ppc40x_system_reset(cpu);
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break;
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}
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}
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6
hw/ppc.h
6
hw/ppc.h
@ -58,9 +58,9 @@ clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq,
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unsigned int decr_excp);
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/* Embedded PowerPC reset */
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void ppc40x_core_reset (CPUPPCState *env);
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void ppc40x_chip_reset (CPUPPCState *env);
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void ppc40x_system_reset (CPUPPCState *env);
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void ppc40x_core_reset(PowerPCCPU *cpu);
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void ppc40x_chip_reset(PowerPCCPU *cpu);
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void ppc40x_system_reset(PowerPCCPU *cpu);
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void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
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extern CPUWriteMemoryFunc * const PPC_io_write[];
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@ -1770,8 +1770,9 @@ static void ppc405_mal_init(CPUPPCState *env, qemu_irq irqs[4])
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/*****************************************************************************/
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/* SPR */
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void ppc40x_core_reset (CPUPPCState *env)
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void ppc40x_core_reset(PowerPCCPU *cpu)
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{
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CPUPPCState *env = &cpu->env;
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target_ulong dbsr;
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printf("Reset PowerPC core\n");
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@ -1782,8 +1783,9 @@ void ppc40x_core_reset (CPUPPCState *env)
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env->spr[SPR_40x_DBSR] = dbsr;
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}
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void ppc40x_chip_reset (CPUPPCState *env)
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void ppc40x_chip_reset(PowerPCCPU *cpu)
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{
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CPUPPCState *env = &cpu->env;
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target_ulong dbsr;
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printf("Reset PowerPC chip\n");
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@ -1795,7 +1797,7 @@ void ppc40x_chip_reset (CPUPPCState *env)
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env->spr[SPR_40x_DBSR] = dbsr;
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}
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void ppc40x_system_reset (CPUPPCState *env)
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void ppc40x_system_reset(PowerPCCPU *cpu)
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{
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printf("Reset PowerPC system\n");
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qemu_system_reset_request();
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@ -1803,21 +1805,23 @@ void ppc40x_system_reset (CPUPPCState *env)
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void store_40x_dbcr0 (CPUPPCState *env, uint32_t val)
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{
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PowerPCCPU *cpu = ppc_env_get_cpu(env);
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switch ((val >> 28) & 0x3) {
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case 0x0:
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/* No action */
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break;
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case 0x1:
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/* Core reset */
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ppc40x_core_reset(env);
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ppc40x_core_reset(cpu);
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break;
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case 0x2:
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/* Chip reset */
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ppc40x_chip_reset(env);
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ppc40x_chip_reset(cpu);
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break;
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case 0x3:
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/* System reset */
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ppc40x_system_reset(env);
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ppc40x_system_reset(cpu);
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break;
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}
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}
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