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target/sparc: Implement UDIVX and SDIVX inline

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Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-10-16 14:35:05 -07:00
parent 89527e3a75
commit f3141174dd
4 changed files with 97 additions and 44 deletions
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24
target/sparc/helper.c
View File

@ -129,30 +129,6 @@ uint64_t helper_sdiv(CPUSPARCState *env, target_ulong a, target_ulong b)
return (uint32_t)r;
}
#ifdef TARGET_SPARC64
int64_t helper_sdivx(CPUSPARCState *env, int64_t a, int64_t b)
{
if (b == 0) {
/* Raise divide by zero trap. */
cpu_raise_exception_ra(env, TT_DIV_ZERO, GETPC());
} else if (b == -1) {
/* Avoid overflow trap with i386 divide insn. */
return -a;
} else {
return a / b;
}
}
uint64_t helper_udivx(CPUSPARCState *env, uint64_t a, uint64_t b)
{
if (b == 0) {
/* Raise divide by zero trap. */
cpu_raise_exception_ra(env, TT_DIV_ZERO, GETPC());
}
return a / b;
}
#endif
target_ulong helper_taddcctv(CPUSPARCState *env, target_ulong src1,
target_ulong src2)
{

4
target/sparc/helper.h
View File

@ -31,10 +31,6 @@ DEF_HELPER_FLAGS_3(udiv, TCG_CALL_NO_WG, i64, env, tl, tl)
DEF_HELPER_FLAGS_3(sdiv, TCG_CALL_NO_WG, i64, env, tl, tl)
DEF_HELPER_3(taddcctv, tl, env, tl, tl)
DEF_HELPER_3(tsubcctv, tl, env, tl, tl)
#ifdef TARGET_SPARC64
DEF_HELPER_FLAGS_3(sdivx, TCG_CALL_NO_WG, s64, env, s64, s64)
DEF_HELPER_FLAGS_3(udivx, TCG_CALL_NO_WG, i64, env, i64, i64)
#endif
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
DEF_HELPER_FLAGS_4(ld_asi, TCG_CALL_NO_WG, i64, env, tl, int, i32)
DEF_HELPER_FLAGS_5(st_asi, TCG_CALL_NO_WG, void, env, tl, i64, int, i32)

4
target/sparc/insns.decode
View File

@ -182,8 +182,8 @@ UMUL 10 ..... 0.1010 ..... . ............. @r_r_ri_cc
SMUL 10 ..... 0.1011 ..... . ............. @r_r_ri_cc
MULScc 10 ..... 100100 ..... . ............. @r_r_ri_cc1
UDIVX 10 ..... 001101 ..... . ............. @r_r_ri_cc0
SDIVX 10 ..... 101101 ..... . ............. @r_r_ri_cc0
UDIVX 10 ..... 001101 ..... . ............. @r_r_ri
SDIVX 10 ..... 101101 ..... . ............. @r_r_ri
UDIV 10 ..... 0.1110 ..... . ............. @r_r_ri_cc
SDIV 10 ..... 0.1111 ..... . ............. @r_r_ri_cc

109
target/sparc/translate.c
View File

@ -51,12 +51,10 @@
# define gen_helper_restored(E) qemu_build_not_reached()
# define gen_helper_retry(E) qemu_build_not_reached()
# define gen_helper_saved(E) qemu_build_not_reached()
# define gen_helper_sdivx(D, E, A, B) qemu_build_not_reached()
# define gen_helper_set_softint(E, S) qemu_build_not_reached()
# define gen_helper_tick_get_count(D, E, T, C) qemu_build_not_reached()
# define gen_helper_tick_set_count(P, S) qemu_build_not_reached()
# define gen_helper_tick_set_limit(P, S) qemu_build_not_reached()
# define gen_helper_udivx(D, E, A, B) qemu_build_not_reached()
# define gen_helper_wrccr(E, S) qemu_build_not_reached()
# define gen_helper_wrcwp(E, S) qemu_build_not_reached()
# define gen_helper_wrgl(E, S) qemu_build_not_reached()
@ -579,16 +577,6 @@ static void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
gen_op_multiply(dst, src1, src2, 1);
}
static void gen_op_udivx(TCGv dst, TCGv src1, TCGv src2)
{
gen_helper_udivx(dst, tcg_env, src1, src2);
}
static void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2)
{
gen_helper_sdivx(dst, tcg_env, src1, src2);
}
static void gen_op_udiv(TCGv dst, TCGv src1, TCGv src2)
{
#ifdef TARGET_SPARC64
@ -3580,8 +3568,6 @@ TRANS(UMUL, MUL, do_logic, a, gen_op_umul, NULL)
TRANS(SMUL, MUL, do_logic, a, gen_op_smul, NULL)
TRANS(MULScc, ALL, do_arith, a, NULL, NULL, gen_op_mulscc)
TRANS(UDIVX, 64, do_arith, a, gen_op_udivx, NULL, NULL)
TRANS(SDIVX, 64, do_arith, a, gen_op_sdivx, NULL, NULL)
TRANS(UDIV, DIV, do_arith, a, gen_op_udiv, NULL, gen_op_udivcc)
TRANS(SDIV, DIV, do_arith, a, gen_op_sdiv, NULL, gen_op_sdivcc)
@ -3605,6 +3591,101 @@ static bool trans_OR(DisasContext *dc, arg_r_r_ri_cc *a)
return do_logic(dc, a, tcg_gen_or_tl, tcg_gen_ori_tl);
}
static bool trans_UDIVX(DisasContext *dc, arg_r_r_ri *a)
{
TCGv dst, src1, src2;
if (!avail_64(dc)) {
return false;
}
/* For simplicity, we under-decoded the rs2 form. */
if (!a->imm && a->rs2_or_imm & ~0x1f) {
return false;
}
if (unlikely(a->rs2_or_imm == 0)) {
gen_exception(dc, TT_DIV_ZERO);
return true;
}
if (a->imm) {
src2 = tcg_constant_tl(a->rs2_or_imm);
} else {
TCGLabel *lab;
finishing_insn(dc);
flush_cond(dc);
lab = delay_exception(dc, TT_DIV_ZERO);
src2 = cpu_regs[a->rs2_or_imm];
tcg_gen_brcondi_tl(TCG_COND_EQ, src2, 0, lab);
}
dst = gen_dest_gpr(dc, a->rd);
src1 = gen_load_gpr(dc, a->rs1);
tcg_gen_divu_tl(dst, src1, src2);
gen_store_gpr(dc, a->rd, dst);
return advance_pc(dc);
}
static bool trans_SDIVX(DisasContext *dc, arg_r_r_ri *a)
{
TCGv dst, src1, src2;
if (!avail_64(dc)) {
return false;
}
/* For simplicity, we under-decoded the rs2 form. */
if (!a->imm && a->rs2_or_imm & ~0x1f) {
return false;
}
if (unlikely(a->rs2_or_imm == 0)) {
gen_exception(dc, TT_DIV_ZERO);
return true;
}
dst = gen_dest_gpr(dc, a->rd);
src1 = gen_load_gpr(dc, a->rs1);
if (a->imm) {
if (unlikely(a->rs2_or_imm == -1)) {
tcg_gen_neg_tl(dst, src1);
gen_store_gpr(dc, a->rd, dst);
return advance_pc(dc);
}
src2 = tcg_constant_tl(a->rs2_or_imm);
} else {
TCGLabel *lab;
TCGv t1, t2;
finishing_insn(dc);
flush_cond(dc);
lab = delay_exception(dc, TT_DIV_ZERO);
src2 = cpu_regs[a->rs2_or_imm];
tcg_gen_brcondi_tl(TCG_COND_EQ, src2, 0, lab);
/*
* Need to avoid INT64_MIN / -1, which will trap on x86 host.
* Set SRC2 to 1 as a new divisor, to produce the correct result.
*/
t1 = tcg_temp_new();
t2 = tcg_temp_new();
tcg_gen_setcondi_tl(TCG_COND_EQ, t1, src1, (target_long)INT64_MIN);
tcg_gen_setcondi_tl(TCG_COND_EQ, t2, src2, -1);
tcg_gen_and_tl(t1, t1, t2);
tcg_gen_movcond_tl(TCG_COND_NE, t1, t1, tcg_constant_tl(0),
tcg_constant_tl(1), src2);
src2 = t1;
}
tcg_gen_div_tl(dst, src1, src2);
gen_store_gpr(dc, a->rd, dst);
return advance_pc(dc);
}
static bool gen_edge(DisasContext *dc, arg_r_r_r *a,
int width, bool cc, bool left)
{