target/arm: Move get_phys_addr_v5 to ptw.c
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220604040607.269301-4-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
8ae0886002
commit
f2d2f5ceb8
@ -10578,8 +10578,7 @@ bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
|
||||
* @ap: The 3-bit access permissions (AP[2:0])
|
||||
* @domain_prot: The 2-bit domain access permissions
|
||||
*/
|
||||
static inline int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx,
|
||||
int ap, int domain_prot)
|
||||
int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap, int domain_prot)
|
||||
{
|
||||
bool is_user = regime_is_user(env, mmu_idx);
|
||||
|
||||
@ -10782,8 +10781,8 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64,
|
||||
return prot_rw | PAGE_EXEC;
|
||||
}
|
||||
|
||||
static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx,
|
||||
uint32_t *table, uint32_t address)
|
||||
bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx,
|
||||
uint32_t *table, uint32_t address)
|
||||
{
|
||||
/* Note that we can only get here for an AArch32 PL0/PL1 lookup */
|
||||
TCR *tcr = regime_tcr(env, mmu_idx);
|
||||
@ -10882,8 +10881,8 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
|
||||
}
|
||||
|
||||
/* All loads done in the course of a page table walk go through here. */
|
||||
static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure,
|
||||
ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi)
|
||||
uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure,
|
||||
ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi)
|
||||
{
|
||||
ARMCPU *cpu = ARM_CPU(cs);
|
||||
CPUARMState *env = &cpu->env;
|
||||
@ -10911,8 +10910,8 @@ static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure,
|
||||
ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi)
|
||||
uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure,
|
||||
ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi)
|
||||
{
|
||||
ARMCPU *cpu = ARM_CPU(cs);
|
||||
CPUARMState *env = &cpu->env;
|
||||
@ -10940,128 +10939,6 @@ static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure,
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
|
||||
MMUAccessType access_type, ARMMMUIdx mmu_idx,
|
||||
hwaddr *phys_ptr, int *prot,
|
||||
target_ulong *page_size,
|
||||
ARMMMUFaultInfo *fi)
|
||||
{
|
||||
CPUState *cs = env_cpu(env);
|
||||
int level = 1;
|
||||
uint32_t table;
|
||||
uint32_t desc;
|
||||
int type;
|
||||
int ap;
|
||||
int domain = 0;
|
||||
int domain_prot;
|
||||
hwaddr phys_addr;
|
||||
uint32_t dacr;
|
||||
|
||||
/* Pagetable walk. */
|
||||
/* Lookup l1 descriptor. */
|
||||
if (!get_level1_table_address(env, mmu_idx, &table, address)) {
|
||||
/* Section translation fault if page walk is disabled by PD0 or PD1 */
|
||||
fi->type = ARMFault_Translation;
|
||||
goto do_fault;
|
||||
}
|
||||
desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
|
||||
mmu_idx, fi);
|
||||
if (fi->type != ARMFault_None) {
|
||||
goto do_fault;
|
||||
}
|
||||
type = (desc & 3);
|
||||
domain = (desc >> 5) & 0x0f;
|
||||
if (regime_el(env, mmu_idx) == 1) {
|
||||
dacr = env->cp15.dacr_ns;
|
||||
} else {
|
||||
dacr = env->cp15.dacr_s;
|
||||
}
|
||||
domain_prot = (dacr >> (domain * 2)) & 3;
|
||||
if (type == 0) {
|
||||
/* Section translation fault. */
|
||||
fi->type = ARMFault_Translation;
|
||||
goto do_fault;
|
||||
}
|
||||
if (type != 2) {
|
||||
level = 2;
|
||||
}
|
||||
if (domain_prot == 0 || domain_prot == 2) {
|
||||
fi->type = ARMFault_Domain;
|
||||
goto do_fault;
|
||||
}
|
||||
if (type == 2) {
|
||||
/* 1Mb section. */
|
||||
phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
|
||||
ap = (desc >> 10) & 3;
|
||||
*page_size = 1024 * 1024;
|
||||
} else {
|
||||
/* Lookup l2 entry. */
|
||||
if (type == 1) {
|
||||
/* Coarse pagetable. */
|
||||
table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
|
||||
} else {
|
||||
/* Fine pagetable. */
|
||||
table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
|
||||
}
|
||||
desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
|
||||
mmu_idx, fi);
|
||||
if (fi->type != ARMFault_None) {
|
||||
goto do_fault;
|
||||
}
|
||||
switch (desc & 3) {
|
||||
case 0: /* Page translation fault. */
|
||||
fi->type = ARMFault_Translation;
|
||||
goto do_fault;
|
||||
case 1: /* 64k page. */
|
||||
phys_addr = (desc & 0xffff0000) | (address & 0xffff);
|
||||
ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
|
||||
*page_size = 0x10000;
|
||||
break;
|
||||
case 2: /* 4k page. */
|
||||
phys_addr = (desc & 0xfffff000) | (address & 0xfff);
|
||||
ap = (desc >> (4 + ((address >> 9) & 6))) & 3;
|
||||
*page_size = 0x1000;
|
||||
break;
|
||||
case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
|
||||
if (type == 1) {
|
||||
/* ARMv6/XScale extended small page format */
|
||||
if (arm_feature(env, ARM_FEATURE_XSCALE)
|
||||
|| arm_feature(env, ARM_FEATURE_V6)) {
|
||||
phys_addr = (desc & 0xfffff000) | (address & 0xfff);
|
||||
*page_size = 0x1000;
|
||||
} else {
|
||||
/* UNPREDICTABLE in ARMv5; we choose to take a
|
||||
* page translation fault.
|
||||
*/
|
||||
fi->type = ARMFault_Translation;
|
||||
goto do_fault;
|
||||
}
|
||||
} else {
|
||||
phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
|
||||
*page_size = 0x400;
|
||||
}
|
||||
ap = (desc >> 4) & 3;
|
||||
break;
|
||||
default:
|
||||
/* Never happens, but compiler isn't smart enough to tell. */
|
||||
g_assert_not_reached();
|
||||
}
|
||||
}
|
||||
*prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
|
||||
*prot |= *prot ? PAGE_EXEC : 0;
|
||||
if (!(*prot & (1 << access_type))) {
|
||||
/* Access permission fault. */
|
||||
fi->type = ARMFault_Permission;
|
||||
goto do_fault;
|
||||
}
|
||||
*phys_ptr = phys_addr;
|
||||
return false;
|
||||
do_fault:
|
||||
fi->domain = domain;
|
||||
fi->level = level;
|
||||
return true;
|
||||
}
|
||||
|
||||
bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
|
||||
MMUAccessType access_type, ARMMMUIdx mmu_idx,
|
||||
hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
|
||||
|
||||
123
target/arm/ptw.c
123
target/arm/ptw.c
@ -13,6 +13,129 @@
|
||||
#include "ptw.h"
|
||||
|
||||
|
||||
static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
|
||||
MMUAccessType access_type, ARMMMUIdx mmu_idx,
|
||||
hwaddr *phys_ptr, int *prot,
|
||||
target_ulong *page_size,
|
||||
ARMMMUFaultInfo *fi)
|
||||
{
|
||||
CPUState *cs = env_cpu(env);
|
||||
int level = 1;
|
||||
uint32_t table;
|
||||
uint32_t desc;
|
||||
int type;
|
||||
int ap;
|
||||
int domain = 0;
|
||||
int domain_prot;
|
||||
hwaddr phys_addr;
|
||||
uint32_t dacr;
|
||||
|
||||
/* Pagetable walk. */
|
||||
/* Lookup l1 descriptor. */
|
||||
if (!get_level1_table_address(env, mmu_idx, &table, address)) {
|
||||
/* Section translation fault if page walk is disabled by PD0 or PD1 */
|
||||
fi->type = ARMFault_Translation;
|
||||
goto do_fault;
|
||||
}
|
||||
desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
|
||||
mmu_idx, fi);
|
||||
if (fi->type != ARMFault_None) {
|
||||
goto do_fault;
|
||||
}
|
||||
type = (desc & 3);
|
||||
domain = (desc >> 5) & 0x0f;
|
||||
if (regime_el(env, mmu_idx) == 1) {
|
||||
dacr = env->cp15.dacr_ns;
|
||||
} else {
|
||||
dacr = env->cp15.dacr_s;
|
||||
}
|
||||
domain_prot = (dacr >> (domain * 2)) & 3;
|
||||
if (type == 0) {
|
||||
/* Section translation fault. */
|
||||
fi->type = ARMFault_Translation;
|
||||
goto do_fault;
|
||||
}
|
||||
if (type != 2) {
|
||||
level = 2;
|
||||
}
|
||||
if (domain_prot == 0 || domain_prot == 2) {
|
||||
fi->type = ARMFault_Domain;
|
||||
goto do_fault;
|
||||
}
|
||||
if (type == 2) {
|
||||
/* 1Mb section. */
|
||||
phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
|
||||
ap = (desc >> 10) & 3;
|
||||
*page_size = 1024 * 1024;
|
||||
} else {
|
||||
/* Lookup l2 entry. */
|
||||
if (type == 1) {
|
||||
/* Coarse pagetable. */
|
||||
table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
|
||||
} else {
|
||||
/* Fine pagetable. */
|
||||
table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
|
||||
}
|
||||
desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
|
||||
mmu_idx, fi);
|
||||
if (fi->type != ARMFault_None) {
|
||||
goto do_fault;
|
||||
}
|
||||
switch (desc & 3) {
|
||||
case 0: /* Page translation fault. */
|
||||
fi->type = ARMFault_Translation;
|
||||
goto do_fault;
|
||||
case 1: /* 64k page. */
|
||||
phys_addr = (desc & 0xffff0000) | (address & 0xffff);
|
||||
ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
|
||||
*page_size = 0x10000;
|
||||
break;
|
||||
case 2: /* 4k page. */
|
||||
phys_addr = (desc & 0xfffff000) | (address & 0xfff);
|
||||
ap = (desc >> (4 + ((address >> 9) & 6))) & 3;
|
||||
*page_size = 0x1000;
|
||||
break;
|
||||
case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
|
||||
if (type == 1) {
|
||||
/* ARMv6/XScale extended small page format */
|
||||
if (arm_feature(env, ARM_FEATURE_XSCALE)
|
||||
|| arm_feature(env, ARM_FEATURE_V6)) {
|
||||
phys_addr = (desc & 0xfffff000) | (address & 0xfff);
|
||||
*page_size = 0x1000;
|
||||
} else {
|
||||
/*
|
||||
* UNPREDICTABLE in ARMv5; we choose to take a
|
||||
* page translation fault.
|
||||
*/
|
||||
fi->type = ARMFault_Translation;
|
||||
goto do_fault;
|
||||
}
|
||||
} else {
|
||||
phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
|
||||
*page_size = 0x400;
|
||||
}
|
||||
ap = (desc >> 4) & 3;
|
||||
break;
|
||||
default:
|
||||
/* Never happens, but compiler isn't smart enough to tell. */
|
||||
g_assert_not_reached();
|
||||
}
|
||||
}
|
||||
*prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
|
||||
*prot |= *prot ? PAGE_EXEC : 0;
|
||||
if (!(*prot & (1 << access_type))) {
|
||||
/* Access permission fault. */
|
||||
fi->type = ARMFault_Permission;
|
||||
goto do_fault;
|
||||
}
|
||||
*phys_ptr = phys_addr;
|
||||
return false;
|
||||
do_fault:
|
||||
fi->domain = domain;
|
||||
fi->level = level;
|
||||
return true;
|
||||
}
|
||||
|
||||
/**
|
||||
* get_phys_addr - get the physical address for this virtual address
|
||||
*
|
||||
|
||||
@ -11,16 +11,21 @@
|
||||
|
||||
#ifndef CONFIG_USER_ONLY
|
||||
|
||||
uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure,
|
||||
ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi);
|
||||
uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure,
|
||||
ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi);
|
||||
|
||||
bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx);
|
||||
bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx);
|
||||
ARMCacheAttrs combine_cacheattrs(CPUARMState *env,
|
||||
ARMCacheAttrs s1, ARMCacheAttrs s2);
|
||||
|
||||
bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
|
||||
MMUAccessType access_type, ARMMMUIdx mmu_idx,
|
||||
hwaddr *phys_ptr, int *prot,
|
||||
target_ulong *page_size,
|
||||
ARMMMUFaultInfo *fi);
|
||||
bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx,
|
||||
uint32_t *table, uint32_t address);
|
||||
int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx,
|
||||
int ap, int domain_prot);
|
||||
|
||||
bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
|
||||
MMUAccessType access_type, ARMMMUIdx mmu_idx,
|
||||
hwaddr *phys_ptr, int *prot,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user