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target/riscv: remove cpu->cfg.ext_s

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Create a new "s" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVS. Instances of cpu->cfg.ext_s and similar are
replaced with riscv_has_ext(env, RVS).

Remove the old "s" property and 'ext_s' from RISCVCPUConfig.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-13-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Daniel Henrique Barboza 2023-04-06 15:03:43 -03:00 committed by Alistair Francis
parent 1a36e23a62
commit f1ea2a52dc
2 changed files with 5 additions and 7 deletions
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11
target/riscv/cpu.c
View File

@ -408,7 +408,6 @@ static void rv64_thead_c906_cpu_init(Object *obj)
cpu->cfg.ext_g = true;
cpu->cfg.ext_u = true;
cpu->cfg.ext_s = true;
cpu->cfg.ext_icsr = true;
cpu->cfg.ext_zfh = true;
cpu->cfg.mmu = true;
@ -843,7 +842,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
return;
}
if (cpu->cfg.ext_s && !cpu->cfg.ext_u) {
if (riscv_has_ext(env, RVS) && !cpu->cfg.ext_u) {
error_setg(errp,
"Setting S extension without U extension is illegal");
return;
@ -855,7 +854,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
return;
}
if (cpu->cfg.ext_h && !cpu->cfg.ext_s) {
if (cpu->cfg.ext_h && !riscv_has_ext(env, RVS)) {
error_setg(errp, "H extension implicitly requires S-mode");
return;
}
@ -1168,7 +1167,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
if (riscv_has_ext(env, RVC)) {
ext |= RVC;
}
if (riscv_cpu_cfg(env)->ext_s) {
if (riscv_has_ext(env, RVS)) {
ext |= RVS;
}
if (riscv_cpu_cfg(env)->ext_u) {
@ -1507,6 +1506,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
.misa_bit = RVE, .enabled = false},
{.name = "m", .description = "Integer multiplication and division",
.misa_bit = RVM, .enabled = true},
{.name = "s", .description = "Supervisor-level instructions",
.misa_bit = RVS, .enabled = true},
};
static void riscv_cpu_add_misa_properties(Object *cpu_obj)
@ -1530,7 +1531,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
static Property riscv_cpu_extensions[] = {
/* Defaults for standard extensions */
DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true),
@ -1647,7 +1647,6 @@ static void register_cpu_props(Object *obj)
*/
if (cpu->env.misa_ext != 0) {
cpu->cfg.ext_v = misa_ext & RVV;
cpu->cfg.ext_s = misa_ext & RVS;
cpu->cfg.ext_u = misa_ext & RVU;
cpu->cfg.ext_h = misa_ext & RVH;
cpu->cfg.ext_j = misa_ext & RVJ;

1
target/riscv/cpu.h
View File

@ -423,7 +423,6 @@ typedef struct {
struct RISCVCPUConfig {
bool ext_g;
bool ext_s;
bool ext_u;
bool ext_h;
bool ext_j;