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target-alpha: convert FP ops to TCG

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- Convert FP ops to TCG
- Fix S format
- Implement F and G formats (untested)
- Fix MF_FPCR an MT_FPCR
- Fix FTOIS, FTOIT, ITOFF, ITOFS, ITOFT
- Fix CPYSN, CPYSE

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5354 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aurel32 2008-09-29 17:21:28 +00:00
parent 023d8ca21f
commit f18cd2238d
11 changed files with 857 additions and 1553 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
target-alpha/cpu.h
View File

@ -277,8 +277,6 @@ struct CPUAlphaState {
*/
target_ulong t0, t1;
#endif
/* */
double ft0, ft1, ft2;
/* Those resources are used only in Qemu core */
CPU_COMMON

3
target-alpha/exec.h
View File

@ -44,9 +44,6 @@ register uint64_t T1 asm(AREG2);
#define PARAM(n) ((uint64_t)PARAM##n)
#define SPARAM(n) ((int32_t)PARAM##n)
#define FT0 (env->ft0)
#define FT1 (env->ft1)
#define FT2 (env->ft2)
#define FP_STATUS (env->fp_status)
#if defined (DEBUG_OP)

6
target-alpha/helper.c
View File

@ -434,12 +434,6 @@ void cpu_dump_state (CPUState *env, FILE *f,
if ((i % 3) == 2)
cpu_fprintf(f, "\n");
}
cpu_fprintf(f, "FT " TARGET_FMT_lx " " TARGET_FMT_lx " " TARGET_FMT_lx,
*((uint64_t *)(&env->ft0)), *((uint64_t *)(&env->ft1)),
*((uint64_t *)(&env->ft2)));
cpu_fprintf(f, "\nMEM " TARGET_FMT_lx " %d %d\n",
ldq_raw(0x000000004007df60ULL),
(uint8_t *)(&env->ft0), (uint8_t *)(&env->fir[0]));
}
void cpu_dump_EA (target_ulong EA)

67
target-alpha/helper.h
View File

@ -41,3 +41,70 @@ DEF_HELPER(uint64_t, helper_mskqh, (int64_t, uint64_t))
DEF_HELPER(uint64_t, helper_insqh, (int64_t, uint64_t))
DEF_HELPER(uint64_t, helper_cmpbge, (uint64_t, uint64_t))
DEF_HELPER(uint64_t, helper_load_fpcr, (void))
DEF_HELPER(void, helper_store_fpcr, (uint64_t val))
DEF_HELPER(uint32_t, helper_f_to_memory, (uint64_t s))
DEF_HELPER(uint64_t, helper_memory_to_f, (uint32_t s))
DEF_HELPER(uint64_t, helper_addf, (uint64_t, uint64_t))
DEF_HELPER(uint64_t, helper_subf, (uint64_t, uint64_t))
DEF_HELPER(uint64_t, helper_mulf, (uint64_t, uint64_t))
DEF_HELPER(uint64_t, helper_divf, (uint64_t, uint64_t))
DEF_HELPER(uint64_t, helper_sqrtf, (uint64_t))
DEF_HELPER(uint64_t, helper_g_to_memory, (uint64_t s))
DEF_HELPER(uint64_t, helper_memory_to_g, (uint64_t s))
DEF_HELPER(uint64_t, helper_addg, (uint64_t, uint64_t))
DEF_HELPER(uint64_t, helper_subg, (uint64_t, uint64_t))
DEF_HELPER(uint64_t, helper_mulg, (uint64_t, uint64_t))
DEF_HELPER(uint64_t, helper_divg, (uint64_t, uint64_t))
DEF_HELPER(uint64_t, helper_sqrtg, (uint64_t))
DEF_HELPER(uint32_t, helper_s_to_memory, (uint64_t s))
DEF_HELPER(uint64_t, helper_memory_to_s, (uint32_t s))
DEF_HELPER(uint64_t, helper_adds, (uint64_t, uint64_t))
DEF_HELPER(uint64_t, helper_subs, (uint64_t, uint64_t))
DEF_HELPER(uint64_t, helper_muls, (uint64_t, uint64_t))
DEF_HELPER(uint64_t, helper_divs, (uint64_t, uint64_t))
DEF_HELPER(uint64_t, helper_sqrts, (uint64_t))
DEF_HELPER(uint64_t, helper_addt, (uint64_t, uint64_t))
DEF_HELPER(uint64_t, helper_subt, (uint64_t, uint64_t))
DEF_HELPER(uint64_t, helper_mult, (uint64_t, uint64_t))
DEF_HELPER(uint64_t, helper_divt, (uint64_t, uint64_t))
DEF_HELPER(uint64_t, helper_sqrtt, (uint64_t))
DEF_HELPER(uint64_t, helper_cmptun, (uint64_t, uint64_t))
DEF_HELPER(uint64_t, helper_cmpteq, (uint64_t, uint64_t))
DEF_HELPER(uint64_t, helper_cmptle, (uint64_t, uint64_t))
DEF_HELPER(uint64_t, helper_cmptlt, (uint64_t, uint64_t))
DEF_HELPER(uint64_t, helper_cmpgeq, (uint64_t, uint64_t))
DEF_HELPER(uint64_t, helper_cmpgle, (uint64_t, uint64_t))
DEF_HELPER(uint64_t, helper_cmpglt, (uint64_t, uint64_t))
DEF_HELPER(uint64_t, helper_cmpfeq, (uint64_t))
DEF_HELPER(uint64_t, helper_cmpfne, (uint64_t))
DEF_HELPER(uint64_t, helper_cmpflt, (uint64_t))
DEF_HELPER(uint64_t, helper_cmpfle, (uint64_t))
DEF_HELPER(uint64_t, helper_cmpfgt, (uint64_t))
DEF_HELPER(uint64_t, helper_cmpfge, (uint64_t))
DEF_HELPER(uint64_t, helper_cpys, (uint64_t, uint64_t))
DEF_HELPER(uint64_t, helper_cpysn, (uint64_t, uint64_t))
DEF_HELPER(uint64_t, helper_cpyse, (uint64_t, uint64_t))
DEF_HELPER(uint64_t, helper_cvtts, (uint64_t))
DEF_HELPER(uint64_t, helper_cvtst, (uint64_t))
DEF_HELPER(uint64_t, helper_cvttq, (uint64_t))
DEF_HELPER(uint32_t, helper_cvtqs, (uint64_t))
DEF_HELPER(uint64_t, helper_cvtqt, (uint64_t))
DEF_HELPER(uint64_t, helper_cvtqf, (uint64_t))
DEF_HELPER(uint64_t, helper_cvtgf, (uint64_t))
DEF_HELPER(uint64_t, helper_cvtgq, (uint64_t))
DEF_HELPER(uint64_t, helper_cvtqg, (uint64_t))
DEF_HELPER(uint64_t, helper_cvtlq, (uint64_t))
DEF_HELPER(uint64_t, helper_cvtql, (uint64_t))
DEF_HELPER(uint64_t, helper_cvtqlv, (uint64_t))
DEF_HELPER(uint64_t, helper_cvtqlsv, (uint64_t))

474
target-alpha/op.c
View File

@ -23,105 +23,8 @@
#include "config.h"
#include "exec.h"
#include "host-utils.h"
#include "op_helper.h"
#define REG 0
#include "op_template.h"
#define REG 1
#include "op_template.h"
#define REG 2
#include "op_template.h"
#define REG 3
#include "op_template.h"
#define REG 4
#include "op_template.h"
#define REG 5
#include "op_template.h"
#define REG 6
#include "op_template.h"
#define REG 7
#include "op_template.h"
#define REG 8
#include "op_template.h"
#define REG 9
#include "op_template.h"
#define REG 10
#include "op_template.h"
#define REG 11
#include "op_template.h"
#define REG 12
#include "op_template.h"
#define REG 13
#include "op_template.h"
#define REG 14
#include "op_template.h"
#define REG 15
#include "op_template.h"
#define REG 16
#include "op_template.h"
#define REG 17
#include "op_template.h"
#define REG 18
#include "op_template.h"
#define REG 19
#include "op_template.h"
#define REG 20
#include "op_template.h"
#define REG 21
#include "op_template.h"
#define REG 22
#include "op_template.h"
#define REG 23
#include "op_template.h"
#define REG 24
#include "op_template.h"
#define REG 25
#include "op_template.h"
#define REG 26
#include "op_template.h"
#define REG 27
#include "op_template.h"
#define REG 28
#include "op_template.h"
#define REG 29
#include "op_template.h"
#define REG 30
#include "op_template.h"
#define REG 31
#include "op_template.h"
/* Debug stuff */
void OPPROTO op_no_op (void)
{
@ -148,383 +51,6 @@ void OPPROTO op_no_op (void)
#include "op_mem.h"
#endif
/* Misc */
void OPPROTO op_load_fpcr (void)
{
helper_load_fpcr();
RETURN();
}
void OPPROTO op_store_fpcr (void)
{
helper_store_fpcr();
RETURN();
}
/* Tests */
#if 0 // Qemu does not know how to do this...
void OPPROTO op_bcond (void)
{
if (T0)
env->pc = T1 & ~3;
else
env->pc = PARAM(1);
RETURN();
}
#else
void OPPROTO op_bcond (void)
{
if (T0)
env->pc = T1 & ~3;
else
env->pc = ((uint64_t)PARAM(1) << 32) | (uint64_t)PARAM(2);
RETURN();
}
#endif
/* IEEE floating point arithmetic */
/* S floating (single) */
void OPPROTO op_adds (void)
{
FT0 = float32_add(FT0, FT1, &FP_STATUS);
RETURN();
}
void OPPROTO op_subs (void)
{
FT0 = float32_sub(FT0, FT1, &FP_STATUS);
RETURN();
}
void OPPROTO op_muls (void)
{
FT0 = float32_mul(FT0, FT1, &FP_STATUS);
RETURN();
}
void OPPROTO op_divs (void)
{
FT0 = float32_div(FT0, FT1, &FP_STATUS);
RETURN();
}
void OPPROTO op_sqrts (void)
{
helper_sqrts();
RETURN();
}
void OPPROTO op_cpys (void)
{
helper_cpys();
RETURN();
}
void OPPROTO op_cpysn (void)
{
helper_cpysn();
RETURN();
}
void OPPROTO op_cpyse (void)
{
helper_cpyse();
RETURN();
}
void OPPROTO op_itofs (void)
{
helper_itofs();
RETURN();
}
void OPPROTO op_ftois (void)
{
helper_ftois();
RETURN();
}
/* T floating (double) */
void OPPROTO op_addt (void)
{
FT0 = float64_add(FT0, FT1, &FP_STATUS);
RETURN();
}
void OPPROTO op_subt (void)
{
FT0 = float64_sub(FT0, FT1, &FP_STATUS);
RETURN();
}
void OPPROTO op_mult (void)
{
FT0 = float64_mul(FT0, FT1, &FP_STATUS);
RETURN();
}
void OPPROTO op_divt (void)
{
FT0 = float64_div(FT0, FT1, &FP_STATUS);
RETURN();
}
void OPPROTO op_sqrtt (void)
{
helper_sqrtt();
RETURN();
}
void OPPROTO op_cmptun (void)
{
helper_cmptun();
RETURN();
}
void OPPROTO op_cmpteq (void)
{
helper_cmpteq();
RETURN();
}
void OPPROTO op_cmptle (void)
{
helper_cmptle();
RETURN();
}
void OPPROTO op_cmptlt (void)
{
helper_cmptlt();
RETURN();
}
void OPPROTO op_itoft (void)
{
helper_itoft();
RETURN();
}
void OPPROTO op_ftoit (void)
{
helper_ftoit();
RETURN();
}
/* VAX floating point arithmetic */
/* F floating */
void OPPROTO op_addf (void)
{
helper_addf();
RETURN();
}
void OPPROTO op_subf (void)
{
helper_subf();
RETURN();
}
void OPPROTO op_mulf (void)
{
helper_mulf();
RETURN();
}
void OPPROTO op_divf (void)
{
helper_divf();
RETURN();
}
void OPPROTO op_sqrtf (void)
{
helper_sqrtf();
RETURN();
}
void OPPROTO op_cmpfeq (void)
{
helper_cmpfeq();
RETURN();
}
void OPPROTO op_cmpfne (void)
{
helper_cmpfne();
RETURN();
}
void OPPROTO op_cmpflt (void)
{
helper_cmpflt();
RETURN();
}
void OPPROTO op_cmpfle (void)
{
helper_cmpfle();
RETURN();
}
void OPPROTO op_cmpfgt (void)
{
helper_cmpfgt();
RETURN();
}
void OPPROTO op_cmpfge (void)
{
helper_cmpfge();
RETURN();
}
void OPPROTO op_itoff (void)
{
helper_itoff();
RETURN();
}
/* G floating */
void OPPROTO op_addg (void)
{
helper_addg();
RETURN();
}
void OPPROTO op_subg (void)
{
helper_subg();
RETURN();
}
void OPPROTO op_mulg (void)
{
helper_mulg();
RETURN();
}
void OPPROTO op_divg (void)
{
helper_divg();
RETURN();
}
void OPPROTO op_sqrtg (void)
{
helper_sqrtg();
RETURN();
}
void OPPROTO op_cmpgeq (void)
{
helper_cmpgeq();
RETURN();
}
void OPPROTO op_cmpglt (void)
{
helper_cmpglt();
RETURN();
}
void OPPROTO op_cmpgle (void)
{
helper_cmpgle();
RETURN();
}
/* Floating point format conversion */
void OPPROTO op_cvtst (void)
{
FT0 = (float)FT0;
RETURN();
}
void OPPROTO op_cvtqs (void)
{
helper_cvtqs();
RETURN();
}
void OPPROTO op_cvtts (void)
{
FT0 = (float)FT0;
RETURN();
}
void OPPROTO op_cvttq (void)
{
helper_cvttq();
RETURN();
}
void OPPROTO op_cvtqt (void)
{
helper_cvtqt();
RETURN();
}
void OPPROTO op_cvtqf (void)
{
helper_cvtqf();
RETURN();
}
void OPPROTO op_cvtgf (void)
{
helper_cvtgf();
RETURN();
}
void OPPROTO op_cvtgd (void)
{
helper_cvtgd();
RETURN();
}
void OPPROTO op_cvtgq (void)
{
helper_cvtgq();
RETURN();
}
void OPPROTO op_cvtqg (void)
{
helper_cvtqg();
RETURN();
}
void OPPROTO op_cvtdg (void)
{
helper_cvtdg();
RETURN();
}
void OPPROTO op_cvtlq (void)
{
helper_cvtlq();
RETURN();
}
void OPPROTO op_cvtql (void)
{
helper_cvtql();
RETURN();
}
void OPPROTO op_cvtqlv (void)
{
helper_cvtqlv();
RETURN();
}
void OPPROTO op_cvtqlsv (void)
{
helper_cvtqlsv();
RETURN();
}
/* PALcode support special instructions */
#if !defined (CONFIG_USER_ONLY)
void OPPROTO op_hw_rei (void)

1111
target-alpha/op_helper.c
View File

File diff suppressed because it is too large Load Diff

59
target-alpha/op_helper.h
View File

@ -19,9 +19,6 @@
*/
void helper_call_pal (uint32_t palcode);
void helper_load_fpcr (void);
void helper_store_fpcr (void);
void helper_cmov_fir (int freg);
double helper_ldff_raw (target_ulong ea);
void helper_stff_raw (target_ulong ea, double op);
@ -42,65 +39,9 @@ double helper_ldfg_data (target_ulong ea);
void helper_stfg_data (target_ulong ea, double op);
#endif
void helper_sqrts (void);
void helper_cpys (void);
void helper_cpysn (void);
void helper_cpyse (void);
void helper_itofs (void);
void helper_ftois (void);
void helper_sqrtt (void);
void helper_cmptun (void);
void helper_cmpteq (void);
void helper_cmptle (void);
void helper_cmptlt (void);
void helper_itoft (void);
void helper_ftoit (void);
void helper_addf (void);
void helper_subf (void);
void helper_mulf (void);
void helper_divf (void);
void helper_sqrtf (void);
void helper_cmpfeq (void);
void helper_cmpfne (void);
void helper_cmpflt (void);
void helper_cmpfle (void);
void helper_cmpfgt (void);
void helper_cmpfge (void);
void helper_itoff (void);
void helper_addg (void);
void helper_subg (void);
void helper_mulg (void);
void helper_divg (void);
void helper_sqrtg (void);
void helper_cmpgeq (void);
void helper_cmpglt (void);
void helper_cmpgle (void);
void helper_cvtqs (void);
void helper_cvttq (void);
void helper_cvtqt (void);
void helper_cvtqf (void);
void helper_cvtgf (void);
void helper_cvtgd (void);
void helper_cvtgq (void);
void helper_cvtqg (void);
void helper_cvtdg (void);
void helper_cvtlq (void);
void helper_cvtql (void);
void helper_cvtqlv (void);
void helper_cvtqlsv (void);
void helper_mfpr (int iprn);
void helper_mtpr (int iprn);
void helper_ld_phys_to_virt (void);
void helper_st_phys_to_virt (void);
void helper_tb_flush (void);
#if defined(HOST_SPARC) || defined(HOST_SPARC64)
void helper_reset_FT0 (void);
void helper_reset_FT1 (void);
void helper_reset_FT2 (void);
#endif

40
target-alpha/op_helper_mem.h
View File

@ -1,40 +0,0 @@
/*
* Alpha emulation cpu micro-operations helpers for memory accesses for qemu.
*
* Copyright (c) 2007 Jocelyn Mayer
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/* XXX: TODO */
double glue(helper_ldff, MEMSUFFIX) (target_ulong ea)
{
return 0;
}
void glue(helper_stff, MEMSUFFIX) (target_ulong ea, double op)
{
}
double glue(helper_ldfg, MEMSUFFIX) (target_ulong ea)
{
return 0;
}
void glue(helper_stfg, MEMSUFFIX) (target_ulong ea, double op)
{
}
#undef MEMSUFFIX

27
target-alpha/op_mem.h
View File

@ -90,31 +90,4 @@ ALPHA_LD_OP(q_l, ldq_l);
ALPHA_ST_OP(l_c, stl_c);
ALPHA_ST_OP(q_c, stq_c);
#define ALPHA_LDF_OP(name, op) \
void OPPROTO glue(glue(op_ld, name), MEMSUFFIX) (void) \
{ \
print_mem_EA(T0); \
FT1 = glue(op, MEMSUFFIX)(T0); \
RETURN(); \
}
#define ALPHA_STF_OP(name, op) \
void OPPROTO glue(glue(op_st, name), MEMSUFFIX) (void) \
{ \
print_mem_EA(T0); \
glue(op, MEMSUFFIX)(T0, FT1); \
RETURN(); \
}
ALPHA_LDF_OP(t, ldfq);
ALPHA_STF_OP(t, stfq);
ALPHA_LDF_OP(s, ldfl);
ALPHA_STF_OP(s, stfl);
/* VAX floating point */
ALPHA_LDF_OP(f, helper_ldff);
ALPHA_STF_OP(f, helper_stff);
ALPHA_LDF_OP(g, helper_ldfg);
ALPHA_STF_OP(g, helper_stfg);
#undef MEMSUFFIX

85
target-alpha/op_template.h
View File

@ -1,85 +0,0 @@
/*
* Alpha emulation cpu micro-operations templates for qemu.
*
* Copyright (c) 2007 Jocelyn Mayer
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/* Optimized constant loads */
#if REG < 3
#if !defined(HOST_SPARC) && !defined(HOST_SPARC64)
void OPPROTO glue(op_reset_FT, REG) (void)
{
glue(FT, REG) = 0;
RETURN();
}
#else
void OPPROTO glue(op_reset_FT, REG) (void)
{
glue(helper_reset_FT, REG)();
RETURN();
}
#endif
#endif /* REG < 3 */
#if REG < 31
/* floating point registers moves */
void OPPROTO glue(op_load_FT0_fir, REG) (void)
{
FT0 = env->fir[REG];
RETURN();
}
void OPPROTO glue(op_load_FT1_fir, REG) (void)
{
FT1 = env->fir[REG];
RETURN();
}
void OPPROTO glue(op_load_FT2_fir, REG) (void)
{
FT2 = env->fir[REG];
RETURN();
}
void OPPROTO glue(op_store_FT0_fir, REG) (void)
{
env->fir[REG] = FT0;
RETURN();
}
void OPPROTO glue(op_store_FT1_fir, REG) (void)
{
env->fir[REG] = FT1;
RETURN();
}
void OPPROTO glue(op_store_FT2_fir, REG) (void)
{
env->fir[REG] = FT2;
RETURN();
}
void OPPROTO glue(op_cmov_fir, REG) (void)
{
helper_cmov_fir(REG);
RETURN();
}
#endif /* REG < 31 */
#undef REG

536
target-alpha/translate.c
View File

@ -48,13 +48,14 @@ struct DisasContext {
/* global register indexes */
static TCGv cpu_env;
static TCGv cpu_ir[31];
static TCGv cpu_fir[31];
static TCGv cpu_pc;
/* dyngen register indexes */
static TCGv cpu_T[2];
/* register names */
static char cpu_reg_names[10*4+21*5];
static char cpu_reg_names[10*4+21*5 + 10*5+21*6];
#include "gen-icount.h"
@ -85,6 +86,11 @@ static void alpha_translate_init(void)
cpu_ir[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
offsetof(CPUState, ir[i]), p);
p += (i < 10) ? 4 : 5;
sprintf(p, "fir%d", i);
cpu_fir[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
offsetof(CPUState, fir[i]), p);
p += (i < 10) ? 5 : 6;
}
cpu_pc = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
@ -105,69 +111,6 @@ static always_inline void gen_op_nop (void)
#endif
}
#define GEN32(func, NAME) \
static GenOpFunc *NAME ## _table [32] = { \
NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
}; \
static always_inline void func (int n) \
{ \
NAME ## _table[n](); \
}
/* FIR moves */
/* Special hacks for fir31 */
#define gen_op_load_FT0_fir31 gen_op_reset_FT0
#define gen_op_load_FT1_fir31 gen_op_reset_FT1
#define gen_op_load_FT2_fir31 gen_op_reset_FT2
#define gen_op_store_FT0_fir31 gen_op_nop
#define gen_op_store_FT1_fir31 gen_op_nop
#define gen_op_store_FT2_fir31 gen_op_nop
#define gen_op_cmov_fir31 gen_op_nop
GEN32(gen_op_load_FT0_fir, gen_op_load_FT0_fir);
GEN32(gen_op_load_FT1_fir, gen_op_load_FT1_fir);
GEN32(gen_op_load_FT2_fir, gen_op_load_FT2_fir);
GEN32(gen_op_store_FT0_fir, gen_op_store_FT0_fir);
GEN32(gen_op_store_FT1_fir, gen_op_store_FT1_fir);
GEN32(gen_op_store_FT2_fir, gen_op_store_FT2_fir);
GEN32(gen_op_cmov_fir, gen_op_cmov_fir);
static always_inline void gen_load_fir (DisasContext *ctx, int firn, int Tn)
{
switch (Tn) {
case 0:
gen_op_load_FT0_fir(firn);
break;
case 1:
gen_op_load_FT1_fir(firn);
break;
case 2:
gen_op_load_FT2_fir(firn);
break;
}
}
static always_inline void gen_store_fir (DisasContext *ctx, int firn, int Tn)
{
switch (Tn) {
case 0:
gen_op_store_FT0_fir(firn);
break;
case 1:
gen_op_store_FT1_fir(firn);
break;
case 2:
gen_op_store_FT2_fir(firn);
break;
}
}
/* Memory moves */
#if defined(CONFIG_USER_ONLY)
#define OP_LD_TABLE(width) \
@ -218,26 +161,6 @@ GEN_ST(l_c);
GEN_LD(q_l);
GEN_ST(q_c);
#if 0 /* currently unused */
GEN_LD(f);
GEN_ST(f);
GEN_LD(g);
GEN_ST(g);
#endif /* 0 */
GEN_LD(s);
GEN_ST(s);
GEN_LD(t);
GEN_ST(t);
static always_inline void _gen_op_bcond (DisasContext *ctx)
{
#if 0 // Qemu does not know how to do this...
gen_op_bcond(ctx->pc);
#else
gen_op_bcond(ctx->pc >> 32, ctx->pc);
#endif
}
static always_inline void gen_excp (DisasContext *ctx,
int exception, int error_code)
{
@ -277,10 +200,34 @@ static always_inline void gen_load_mem_dyngen (DisasContext *ctx,
}
}
static always_inline void gen_qemu_ldf (TCGv t0, TCGv t1, int flags)
{
TCGv tmp = tcg_temp_new(TCG_TYPE_I32);
tcg_gen_qemu_ld32u(tmp, t1, flags);
tcg_gen_helper_1_1(helper_memory_to_f, t0, tmp);
tcg_temp_free(tmp);
}
static always_inline void gen_qemu_ldg (TCGv t0, TCGv t1, int flags)
{
TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
tcg_gen_qemu_ld64(tmp, t1, flags);
tcg_gen_helper_1_1(helper_memory_to_g, t0, tmp);
tcg_temp_free(tmp);
}
static always_inline void gen_qemu_lds (TCGv t0, TCGv t1, int flags)
{
TCGv tmp = tcg_temp_new(TCG_TYPE_I32);
tcg_gen_qemu_ld32u(tmp, t1, flags);
tcg_gen_helper_1_1(helper_memory_to_s, t0, tmp);
tcg_temp_free(tmp);
}
static always_inline void gen_load_mem (DisasContext *ctx,
void (*tcg_gen_qemu_load)(TCGv t0, TCGv t1, int flags),
int ra, int rb, int32_t disp16,
int clear)
int fp, int clear)
{
TCGv addr;
@ -297,7 +244,10 @@ static always_inline void gen_load_mem (DisasContext *ctx,
disp16 &= ~0x7;
tcg_gen_movi_i64(addr, disp16);
}
tcg_gen_qemu_load(cpu_ir[ra], addr, ctx->mem_idx);
if (fp)
tcg_gen_qemu_load(cpu_fir[ra], addr, ctx->mem_idx);
else
tcg_gen_qemu_load(cpu_ir[ra], addr, ctx->mem_idx);
tcg_temp_free(addr);
}
@ -319,10 +269,34 @@ static always_inline void gen_store_mem_dyngen (DisasContext *ctx,
(*gen_store_op)(ctx);
}
static always_inline void gen_qemu_stf (TCGv t0, TCGv t1, int flags)
{
TCGv tmp = tcg_temp_new(TCG_TYPE_I32);
tcg_gen_helper_1_1(helper_f_to_memory, tmp, t0);
tcg_gen_qemu_st32(tmp, t1, flags);
tcg_temp_free(tmp);
}
static always_inline void gen_qemu_stg (TCGv t0, TCGv t1, int flags)
{
TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
tcg_gen_helper_1_1(helper_g_to_memory, tmp, t0);
tcg_gen_qemu_st64(tmp, t1, flags);
tcg_temp_free(tmp);
}
static always_inline void gen_qemu_sts (TCGv t0, TCGv t1, int flags)
{
TCGv tmp = tcg_temp_new(TCG_TYPE_I32);
tcg_gen_helper_1_1(helper_s_to_memory, tmp, t0);
tcg_gen_qemu_st32(tmp, t1, flags);
tcg_temp_free(tmp);
}
static always_inline void gen_store_mem (DisasContext *ctx,
void (*tcg_gen_qemu_store)(TCGv t0, TCGv t1, int flags),
int ra, int rb, int32_t disp16,
int clear)
int fp, int clear)
{
TCGv addr = tcg_temp_new(TCG_TYPE_I64);
if (rb != 31) {
@ -334,9 +308,12 @@ static always_inline void gen_store_mem (DisasContext *ctx,
disp16 &= ~0x7;
tcg_gen_movi_i64(addr, disp16);
}
if (ra != 31)
tcg_gen_qemu_store(cpu_ir[ra], addr, ctx->mem_idx);
else {
if (ra != 31) {
if (fp)
tcg_gen_qemu_store(cpu_fir[ra], addr, ctx->mem_idx);
else
tcg_gen_qemu_store(cpu_ir[ra], addr, ctx->mem_idx);
} else {
TCGv zero = tcg_const_i64(0);
tcg_gen_qemu_store(zero, addr, ctx->mem_idx);
tcg_temp_free(zero);
@ -344,30 +321,6 @@ static always_inline void gen_store_mem (DisasContext *ctx,
tcg_temp_free(addr);
}
static always_inline void gen_load_fmem (DisasContext *ctx,
void (*gen_load_fop)(DisasContext *ctx),
int ra, int rb, int32_t disp16)
{
if (rb != 31)
tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp16);
else
tcg_gen_movi_i64(cpu_T[0], disp16);
(*gen_load_fop)(ctx);
gen_store_fir(ctx, ra, 1);
}
static always_inline void gen_store_fmem (DisasContext *ctx,
void (*gen_store_fop)(DisasContext *ctx),
int ra, int rb, int32_t disp16)
{
if (rb != 31)
tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp16);
else
tcg_gen_movi_i64(cpu_T[0], disp16);
gen_load_fir(ctx, ra, 1);
(*gen_store_fop)(ctx);
}
static always_inline void gen_bcond (DisasContext *ctx,
TCGCond cond,
int ra, int32_t disp16, int mask)
@ -398,13 +351,27 @@ static always_inline void gen_bcond (DisasContext *ctx,
}
static always_inline void gen_fbcond (DisasContext *ctx,
void (*gen_test_op)(void),
void* func,
int ra, int32_t disp16)
{
tcg_gen_movi_i64(cpu_T[1], ctx->pc + (int64_t)(disp16 << 2));
gen_load_fir(ctx, ra, 0);
(*gen_test_op)();
_gen_op_bcond(ctx);
int l1, l2;
TCGv tmp;
l1 = gen_new_label();
l2 = gen_new_label();
if (ra != 31) {
tmp = tcg_temp_new(TCG_TYPE_I64);
tcg_gen_helper_1_1(func, tmp, cpu_fir[ra]);
} else {
tmp = tcg_const_i64(0);
tcg_gen_helper_1_1(func, tmp, tmp);
}
tcg_gen_brcondi_i64(TCG_COND_NE, tmp, 0, l1);
tcg_gen_movi_i64(cpu_pc, ctx->pc);
tcg_gen_br(l2);
gen_set_label(l1);
tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp16 << 2));
gen_set_label(l2);
}
static always_inline void gen_cmov (DisasContext *ctx,
@ -441,55 +408,69 @@ static always_inline void gen_cmov (DisasContext *ctx,
gen_set_label(l1);
}
static always_inline void gen_farith2 (DisasContext *ctx,
void (*gen_arith_fop)(void),
static always_inline void gen_farith2 (void *helper,
int rb, int rc)
{
gen_load_fir(ctx, rb, 0);
(*gen_arith_fop)();
gen_store_fir(ctx, rc, 0);
if (unlikely(rc == 31))
return;
if (rb != 31)
tcg_gen_helper_1_1(helper, cpu_fir[rc], cpu_fir[rb]);
else {
TCGv tmp = tcg_const_i64(0);
tcg_gen_helper_1_1(helper, cpu_fir[rc], tmp);
tcg_temp_free(tmp);
}
}
static always_inline void gen_farith3 (DisasContext *ctx,
void (*gen_arith_fop)(void),
static always_inline void gen_farith3 (void *helper,
int ra, int rb, int rc)
{
gen_load_fir(ctx, ra, 0);
gen_load_fir(ctx, rb, 1);
(*gen_arith_fop)();
gen_store_fir(ctx, rc, 0);
if (unlikely(rc == 31))
return;
if (ra != 31) {
if (rb != 31)
tcg_gen_helper_1_2(helper, cpu_fir[rc], cpu_fir[ra], cpu_fir[rb]);
else {
TCGv tmp = tcg_const_i64(0);
tcg_gen_helper_1_2(helper, cpu_fir[rc], cpu_fir[ra], tmp);
tcg_temp_free(tmp);
}
} else {
TCGv tmp = tcg_const_i64(0);
if (rb != 31)
tcg_gen_helper_1_2(helper, cpu_fir[rc], tmp, cpu_fir[rb]);
else
tcg_gen_helper_1_2(helper, cpu_fir[rc], tmp, tmp);
tcg_temp_free(tmp);
}
}
static always_inline void gen_fcmov (DisasContext *ctx,
void (*gen_test_fop)(void),
static always_inline void gen_fcmov (void *func,
int ra, int rb, int rc)
{
gen_load_fir(ctx, ra, 0);
gen_load_fir(ctx, rb, 1);
(*gen_test_fop)();
gen_op_cmov_fir(rc);
}
int l1;
TCGv tmp;
static always_inline void gen_fti (DisasContext *ctx,
void (*gen_move_fop)(void),
int ra, int rc)
{
gen_load_fir(ctx, rc, 0);
(*gen_move_fop)();
if (ra != 31)
tcg_gen_mov_i64(cpu_ir[ra], cpu_T[0]);
}
if (unlikely(rc == 31))
return;
static always_inline void gen_itf (DisasContext *ctx,
void (*gen_move_fop)(void),
int ra, int rc)
{
if (ra != 31)
tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]);
l1 = gen_new_label();
tmp = tcg_temp_new(TCG_TYPE_I64);
if (ra != 31) {
tmp = tcg_temp_new(TCG_TYPE_I64);
tcg_gen_helper_1_1(func, tmp, cpu_fir[ra]);
} else {
tmp = tcg_const_i64(0);
tcg_gen_helper_1_1(func, tmp, tmp);
}
tcg_gen_brcondi_i64(TCG_COND_EQ, tmp, 0, l1);
if (rb != 31)
tcg_gen_mov_i64(cpu_fir[rc], cpu_fir[ra]);
else
tcg_gen_movi_i64(cpu_T[0], 0);
(*gen_move_fop)();
gen_store_fir(ctx, rc, 0);
tcg_gen_movi_i64(cpu_fir[rc], 0);
gen_set_label(l1);
}
/* EXTWH, EXTWH, EXTLH, EXTQH */
@ -704,29 +685,29 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
/* LDBU */
if (!(ctx->amask & AMASK_BWX))
goto invalid_opc;
gen_load_mem(ctx, &tcg_gen_qemu_ld8u, ra, rb, disp16, 0);
gen_load_mem(ctx, &tcg_gen_qemu_ld8u, ra, rb, disp16, 0, 0);
break;
case 0x0B:
/* LDQ_U */
gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 1);
gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 0, 1);
break;
case 0x0C:
/* LDWU */
if (!(ctx->amask & AMASK_BWX))
goto invalid_opc;
gen_load_mem(ctx, &tcg_gen_qemu_ld16u, ra, rb, disp16, 1);
gen_load_mem(ctx, &tcg_gen_qemu_ld16u, ra, rb, disp16, 0, 1);
break;
case 0x0D:
/* STW */
gen_store_mem(ctx, &tcg_gen_qemu_st16, ra, rb, disp16, 0);
gen_store_mem(ctx, &tcg_gen_qemu_st16, ra, rb, disp16, 0, 0);
break;
case 0x0E:
/* STB */
gen_store_mem(ctx, &tcg_gen_qemu_st8, ra, rb, disp16, 0);
gen_store_mem(ctx, &tcg_gen_qemu_st8, ra, rb, disp16, 0, 0);
break;
case 0x0F:
/* STQ_U */
gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 1);
gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0, 1);
break;
case 0x10:
switch (fn7) {
@ -1349,47 +1330,64 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
/* ITOFS */
if (!(ctx->amask & AMASK_FIX))
goto invalid_opc;
gen_itf(ctx, &gen_op_itofs, ra, rc);
if (likely(rc != 31)) {
if (ra != 31) {
TCGv tmp = tcg_temp_new(TCG_TYPE_I32);
tcg_gen_trunc_i64_i32(tmp, cpu_ir[ra]);
tcg_gen_helper_1_1(helper_memory_to_s, cpu_fir[rc], tmp);
tcg_temp_free(tmp);
} else
tcg_gen_movi_i64(cpu_fir[rc], 0);
}
break;
case 0x0A:
/* SQRTF */
if (!(ctx->amask & AMASK_FIX))
goto invalid_opc;
gen_farith2(ctx, &gen_op_sqrtf, rb, rc);
gen_farith2(&helper_sqrtf, rb, rc);
break;
case 0x0B:
/* SQRTS */
if (!(ctx->amask & AMASK_FIX))
goto invalid_opc;
gen_farith2(ctx, &gen_op_sqrts, rb, rc);
gen_farith2(&helper_sqrts, rb, rc);
break;
case 0x14:
/* ITOFF */
if (!(ctx->amask & AMASK_FIX))
goto invalid_opc;
#if 0 // TODO
gen_itf(ctx, &gen_op_itoff, ra, rc);
#else
goto invalid_opc;
#endif
if (likely(rc != 31)) {
if (ra != 31) {
TCGv tmp = tcg_temp_new(TCG_TYPE_I32);
tcg_gen_trunc_i64_i32(tmp, cpu_ir[ra]);
tcg_gen_helper_1_1(helper_memory_to_f, cpu_fir[rc], tmp);
tcg_temp_free(tmp);
} else
tcg_gen_movi_i64(cpu_fir[rc], 0);
}
break;
case 0x24:
/* ITOFT */
if (!(ctx->amask & AMASK_FIX))
goto invalid_opc;
gen_itf(ctx, &gen_op_itoft, ra, rc);
if (likely(rc != 31)) {
if (ra != 31)
tcg_gen_mov_i64(cpu_fir[rc], cpu_ir[ra]);
else
tcg_gen_movi_i64(cpu_fir[rc], 0);
}
break;
case 0x2A:
/* SQRTG */
if (!(ctx->amask & AMASK_FIX))
goto invalid_opc;
gen_farith2(ctx, &gen_op_sqrtg, rb, rc);
gen_farith2(&helper_sqrtg, rb, rc);
break;
case 0x02B:
/* SQRTT */
if (!(ctx->amask & AMASK_FIX))
goto invalid_opc;
gen_farith2(ctx, &gen_op_sqrtt, rb, rc);
gen_farith2(&helper_sqrtt, rb, rc);
break;
default:
goto invalid_opc;
@ -1401,79 +1399,79 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
switch (fpfn) { /* f11 & 0x3F */
case 0x00:
/* ADDF */
gen_farith3(ctx, &gen_op_addf, ra, rb, rc);
gen_farith3(&helper_addf, ra, rb, rc);
break;
case 0x01:
/* SUBF */
gen_farith3(ctx, &gen_op_subf, ra, rb, rc);
gen_farith3(&helper_subf, ra, rb, rc);
break;
case 0x02:
/* MULF */
gen_farith3(ctx, &gen_op_mulf, ra, rb, rc);
gen_farith3(&helper_mulf, ra, rb, rc);
break;
case 0x03:
/* DIVF */
gen_farith3(ctx, &gen_op_divf, ra, rb, rc);
gen_farith3(&helper_divf, ra, rb, rc);
break;
case 0x1E:
/* CVTDG */
#if 0 // TODO
gen_farith2(ctx, &gen_op_cvtdg, rb, rc);
gen_farith2(&helper_cvtdg, rb, rc);
#else
goto invalid_opc;
#endif
break;
case 0x20:
/* ADDG */
gen_farith3(ctx, &gen_op_addg, ra, rb, rc);
gen_farith3(&helper_addg, ra, rb, rc);
break;
case 0x21:
/* SUBG */
gen_farith3(ctx, &gen_op_subg, ra, rb, rc);
gen_farith3(&helper_subg, ra, rb, rc);
break;
case 0x22:
/* MULG */
gen_farith3(ctx, &gen_op_mulg, ra, rb, rc);
gen_farith3(&helper_mulg, ra, rb, rc);
break;
case 0x23:
/* DIVG */
gen_farith3(ctx, &gen_op_divg, ra, rb, rc);
gen_farith3(&helper_divg, ra, rb, rc);
break;
case 0x25:
/* CMPGEQ */
gen_farith3(ctx, &gen_op_cmpgeq, ra, rb, rc);
gen_farith3(&helper_cmpgeq, ra, rb, rc);
break;
case 0x26:
/* CMPGLT */
gen_farith3(ctx, &gen_op_cmpglt, ra, rb, rc);
gen_farith3(&helper_cmpglt, ra, rb, rc);
break;
case 0x27:
/* CMPGLE */
gen_farith3(ctx, &gen_op_cmpgle, ra, rb, rc);
gen_farith3(&helper_cmpgle, ra, rb, rc);
break;
case 0x2C:
/* CVTGF */
gen_farith2(ctx, &gen_op_cvtgf, rb, rc);
gen_farith2(&helper_cvtgf, rb, rc);
break;
case 0x2D:
/* CVTGD */
#if 0 // TODO
gen_farith2(ctx, &gen_op_cvtgd, rb, rc);
gen_farith2(ctx, &helper_cvtgd, rb, rc);
#else
goto invalid_opc;
#endif
break;
case 0x2F:
/* CVTGQ */
gen_farith2(ctx, &gen_op_cvtgq, rb, rc);
gen_farith2(&helper_cvtgq, rb, rc);
break;
case 0x3C:
/* CVTQF */
gen_farith2(ctx, &gen_op_cvtqf, rb, rc);
gen_farith2(&helper_cvtqf, rb, rc);
break;
case 0x3E:
/* CVTQG */
gen_farith2(ctx, &gen_op_cvtqg, rb, rc);
gen_farith2(&helper_cvtqg, rb, rc);
break;
default:
goto invalid_opc;
@ -1485,73 +1483,73 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
switch (fpfn) { /* f11 & 0x3F */
case 0x00:
/* ADDS */
gen_farith3(ctx, &gen_op_adds, ra, rb, rc);
gen_farith3(&helper_adds, ra, rb, rc);
break;
case 0x01:
/* SUBS */
gen_farith3(ctx, &gen_op_subs, ra, rb, rc);
gen_farith3(&helper_subs, ra, rb, rc);
break;
case 0x02:
/* MULS */
gen_farith3(ctx, &gen_op_muls, ra, rb, rc);
gen_farith3(&helper_muls, ra, rb, rc);
break;
case 0x03:
/* DIVS */
gen_farith3(ctx, &gen_op_divs, ra, rb, rc);
gen_farith3(&helper_divs, ra, rb, rc);
break;
case 0x20:
/* ADDT */
gen_farith3(ctx, &gen_op_addt, ra, rb, rc);
gen_farith3(&helper_addt, ra, rb, rc);
break;
case 0x21:
/* SUBT */
gen_farith3(ctx, &gen_op_subt, ra, rb, rc);
gen_farith3(&helper_subt, ra, rb, rc);
break;
case 0x22:
/* MULT */
gen_farith3(ctx, &gen_op_mult, ra, rb, rc);
gen_farith3(&helper_mult, ra, rb, rc);
break;
case 0x23:
/* DIVT */
gen_farith3(ctx, &gen_op_divt, ra, rb, rc);
gen_farith3(&helper_divt, ra, rb, rc);
break;
case 0x24:
/* CMPTUN */
gen_farith3(ctx, &gen_op_cmptun, ra, rb, rc);
gen_farith3(&helper_cmptun, ra, rb, rc);
break;
case 0x25:
/* CMPTEQ */
gen_farith3(ctx, &gen_op_cmpteq, ra, rb, rc);
gen_farith3(&helper_cmpteq, ra, rb, rc);
break;
case 0x26:
/* CMPTLT */
gen_farith3(ctx, &gen_op_cmptlt, ra, rb, rc);
gen_farith3(&helper_cmptlt, ra, rb, rc);
break;
case 0x27:
/* CMPTLE */
gen_farith3(ctx, &gen_op_cmptle, ra, rb, rc);
gen_farith3(&helper_cmptle, ra, rb, rc);
break;
case 0x2C:
/* XXX: incorrect */
if (fn11 == 0x2AC) {
/* CVTST */
gen_farith2(ctx, &gen_op_cvtst, rb, rc);
gen_farith2(&helper_cvtst, rb, rc);
} else {
/* CVTTS */
gen_farith2(ctx, &gen_op_cvtts, rb, rc);
gen_farith2(&helper_cvtts, rb, rc);
}
break;
case 0x2F:
/* CVTTQ */
gen_farith2(ctx, &gen_op_cvttq, rb, rc);
gen_farith2(&helper_cvttq, rb, rc);
break;
case 0x3C:
/* CVTQS */
gen_farith2(ctx, &gen_op_cvtqs, rb, rc);
gen_farith2(&helper_cvtqs, rb, rc);
break;
case 0x3E:
/* CVTQT */
gen_farith2(ctx, &gen_op_cvtqt, rb, rc);
gen_farith2(&helper_cvtqt, rb, rc);
break;
default:
goto invalid_opc;
@ -1561,76 +1559,76 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
switch (fn11) {
case 0x010:
/* CVTLQ */
gen_farith2(ctx, &gen_op_cvtlq, rb, rc);
gen_farith2(&helper_cvtlq, rb, rc);
break;
case 0x020:
/* CPYS */
if (ra == rb) {
if (ra == 31 && rc == 31) {
/* FNOP */
gen_op_nop();
} else {
if (likely(rc != 31)) {
if (ra == rb)
/* FMOV */
gen_load_fir(ctx, rb, 0);
gen_store_fir(ctx, rc, 0);
}
} else {
gen_farith3(ctx, &gen_op_cpys, ra, rb, rc);
tcg_gen_mov_i64(cpu_fir[rc], cpu_fir[ra]);
else
/* CPYS */
gen_farith3(&helper_cpys, ra, rb, rc);
}
break;
case 0x021:
/* CPYSN */
gen_farith2(ctx, &gen_op_cpysn, rb, rc);
gen_farith3(&helper_cpysn, ra, rb, rc);
break;
case 0x022:
/* CPYSE */
gen_farith2(ctx, &gen_op_cpyse, rb, rc);
gen_farith3(&helper_cpyse, ra, rb, rc);
break;
case 0x024:
/* MT_FPCR */
gen_load_fir(ctx, ra, 0);
gen_op_store_fpcr();
if (likely(ra != 31))
tcg_gen_helper_0_1(helper_store_fpcr, cpu_fir[ra]);
else {
TCGv tmp = tcg_const_i64(0);
tcg_gen_helper_0_1(helper_store_fpcr, tmp);
tcg_temp_free(tmp);
}
break;
case 0x025:
/* MF_FPCR */
gen_op_load_fpcr();
gen_store_fir(ctx, ra, 0);
if (likely(ra != 31))
tcg_gen_helper_1_0(helper_load_fpcr, cpu_fir[ra]);
break;
case 0x02A:
/* FCMOVEQ */
gen_fcmov(ctx, &gen_op_cmpfeq, ra, rb, rc);
gen_fcmov(&helper_cmpfeq, ra, rb, rc);
break;
case 0x02B:
/* FCMOVNE */
gen_fcmov(ctx, &gen_op_cmpfne, ra, rb, rc);
gen_fcmov(&helper_cmpfne, ra, rb, rc);
break;
case 0x02C:
/* FCMOVLT */
gen_fcmov(ctx, &gen_op_cmpflt, ra, rb, rc);
gen_fcmov(&helper_cmpflt, ra, rb, rc);
break;
case 0x02D:
/* FCMOVGE */
gen_fcmov(ctx, &gen_op_cmpfge, ra, rb, rc);
gen_fcmov(&helper_cmpfge, ra, rb, rc);
break;
case 0x02E:
/* FCMOVLE */
gen_fcmov(ctx, &gen_op_cmpfle, ra, rb, rc);
gen_fcmov(&helper_cmpfle, ra, rb, rc);
break;
case 0x02F:
/* FCMOVGT */
gen_fcmov(ctx, &gen_op_cmpfgt, ra, rb, rc);
gen_fcmov(&helper_cmpfgt, ra, rb, rc);
break;
case 0x030:
/* CVTQL */
gen_farith2(ctx, &gen_op_cvtql, rb, rc);
gen_farith2(&helper_cvtql, rb, rc);
break;
case 0x130:
/* CVTQL/V */
gen_farith2(ctx, &gen_op_cvtqlv, rb, rc);
gen_farith2(&helper_cvtqlv, rb, rc);
break;
case 0x530:
/* CVTQL/SV */
gen_farith2(ctx, &gen_op_cvtqlsv, rb, rc);
gen_farith2(&helper_cvtqlsv, rb, rc);
break;
default:
goto invalid_opc;
@ -1981,13 +1979,29 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
/* FTOIT */
if (!(ctx->amask & AMASK_FIX))
goto invalid_opc;
gen_fti(ctx, &gen_op_ftoit, ra, rb);
if (likely(rc != 31)) {
if (ra != 31)
tcg_gen_mov_i64(cpu_ir[rc], cpu_fir[ra]);
else
tcg_gen_movi_i64(cpu_ir[rc], 0);
}
break;
case 0x78:
/* FTOIS */
if (!(ctx->amask & AMASK_FIX))
goto invalid_opc;
gen_fti(ctx, &gen_op_ftois, ra, rb);
if (rc != 31) {
TCGv tmp1 = tcg_temp_new(TCG_TYPE_I32);
if (ra != 31)
tcg_gen_helper_1_1(helper_s_to_memory, tmp1, cpu_fir[ra]);
else {
TCGv tmp2 = tcg_const_i64(0);
tcg_gen_helper_1_1(helper_s_to_memory, tmp1, tmp2);
tcg_temp_free(tmp2);
}
tcg_gen_ext_i32_i64(cpu_ir[rc], tmp1);
tcg_temp_free(tmp1);
}
break;
default:
goto invalid_opc;
@ -2116,59 +2130,43 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
#endif
case 0x20:
/* LDF */
#if 0 // TODO
gen_load_fmem(ctx, &gen_ldf, ra, rb, disp16);
#else
goto invalid_opc;
#endif
gen_load_mem(ctx, &gen_qemu_ldf, ra, rb, disp16, 1, 0);
break;
case 0x21:
/* LDG */
#if 0 // TODO
gen_load_fmem(ctx, &gen_ldg, ra, rb, disp16);
#else
goto invalid_opc;
#endif
gen_load_mem(ctx, &gen_qemu_ldg, ra, rb, disp16, 1, 0);
break;
case 0x22:
/* LDS */
gen_load_fmem(ctx, &gen_lds, ra, rb, disp16);
gen_load_mem(ctx, &gen_qemu_lds, ra, rb, disp16, 1, 0);
break;
case 0x23:
/* LDT */
gen_load_fmem(ctx, &gen_ldt, ra, rb, disp16);
gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 1, 0);
break;
case 0x24:
/* STF */
#if 0 // TODO
gen_store_fmem(ctx, &gen_stf, ra, rb, disp16);
#else
goto invalid_opc;
#endif
gen_store_mem(ctx, &gen_qemu_stf, ra, rb, disp16, 1, 0);
break;
case 0x25:
/* STG */
#if 0 // TODO
gen_store_fmem(ctx, &gen_stg, ra, rb, disp16);
#else
goto invalid_opc;
#endif
gen_store_mem(ctx, &gen_qemu_stg, ra, rb, disp16, 1, 0);
break;
case 0x26:
/* STS */
gen_store_fmem(ctx, &gen_sts, ra, rb, disp16);
gen_store_mem(ctx, &gen_qemu_sts, ra, rb, disp16, 1, 0);
break;
case 0x27:
/* STT */
gen_store_fmem(ctx, &gen_stt, ra, rb, disp16);
gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 1, 0);
break;
case 0x28:
/* LDL */
gen_load_mem(ctx, &tcg_gen_qemu_ld32s, ra, rb, disp16, 0);
gen_load_mem(ctx, &tcg_gen_qemu_ld32s, ra, rb, disp16, 0, 0);
break;
case 0x29:
/* LDQ */
gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 0);
gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 0, 0);
break;
case 0x2A:
/* LDL_L */
@ -2180,11 +2178,11 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
break;
case 0x2C:
/* STL */
gen_store_mem(ctx, &tcg_gen_qemu_st32, ra, rb, disp16, 0);
gen_store_mem(ctx, &tcg_gen_qemu_st32, ra, rb, disp16, 0, 0);
break;
case 0x2D:
/* STQ */
gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0);
gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0, 0);
break;
case 0x2E:
/* STL_C */
@ -2203,17 +2201,17 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
break;
case 0x31:
/* FBEQ */
gen_fbcond(ctx, &gen_op_cmpfeq, ra, disp16);
gen_fbcond(ctx, &helper_cmpfeq, ra, disp16);
ret = 1;
break;
case 0x32:
/* FBLT */
gen_fbcond(ctx, &gen_op_cmpflt, ra, disp16);
gen_fbcond(ctx, &helper_cmpflt, ra, disp16);
ret = 1;
break;
case 0x33:
/* FBLE */
gen_fbcond(ctx, &gen_op_cmpfle, ra, disp16);
gen_fbcond(ctx, &helper_cmpfle, ra, disp16);
ret = 1;
break;
case 0x34:
@ -2225,17 +2223,17 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
break;
case 0x35:
/* FBNE */
gen_fbcond(ctx, &gen_op_cmpfne, ra, disp16);
gen_fbcond(ctx, &helper_cmpfne, ra, disp16);
ret = 1;
break;
case 0x36:
/* FBGE */
gen_fbcond(ctx, &gen_op_cmpfge, ra, disp16);
gen_fbcond(ctx, &helper_cmpfge, ra, disp16);
ret = 1;
break;
case 0x37:
/* FBGT */
gen_fbcond(ctx, &gen_op_cmpfgt, ra, disp16);
gen_fbcond(ctx, &helper_cmpfgt, ra, disp16);
ret = 1;
break;
case 0x38: