trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
Privileged spec section 4.1.9 mentions: "When a trap is taken into S-mode, stval is written with exception-specific information to assist software in handling the trap. (...) If stval is written with a nonzero value when a breakpoint, address-misaligned, access-fault, or page-fault exception occurs on an instruction fetch, load, or store, then stval will contain the faulting virtual address." A similar text is found for mtval in section 3.1.16. Setting mtval/stval in this scenario is optional, but some softwares read these regs when handling ebreaks. Write 'badaddr' in all ebreak breakpoints to write the appropriate 'tval' during riscv_do_cpu_interrrupt(). Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240416230437.1869024-3-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -62,6 +62,8 @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
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if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
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generate_exception(ctx, RISCV_EXCP_SEMIHOST);
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} else {
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tcg_gen_st_tl(tcg_constant_tl(ebreak_addr), tcg_env,
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offsetof(CPURISCVState, badaddr));
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generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
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}
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return true;
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