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hw/arm/smmuv3: Fix IIDR offset

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The SMMU IIDR register is at 0x018 offset.

Fixes: 10a83cb988 ("hw/arm/smmuv3: Skeleton")
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200728150815.11446-9-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Eric Auger 2020-07-28 17:08:12 +02:00 committed by Peter Maydell
parent d52915616c
commit f0ec277cd4
1 changed files with 1 additions and 1 deletions
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hw/arm/smmuv3-internal.h
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@ -63,7 +63,7 @@ REG32(IDR5, 0x14)
#define SMMU_IDR5_OAS 4
REG32(IIDR, 0x1c)
REG32(IIDR, 0x18)
REG32(CR0, 0x20)
FIELD(CR0, SMMU_ENABLE, 0, 1)
FIELD(CR0, EVENTQEN, 2, 1)