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usb: hcd-xhci-sysbus: Attach xhci to sysbus device

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Use XHCI as sysbus device, add memory region property to get the
address space instance for dma read/write.

Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Message-id: 1600957256-6494-5-git-send-email-sai.pavan.boddu@xilinx.com
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
This commit is contained in:
Sai Pavan Boddu 2020-09-24 19:50:53 +05:30 committed by Gerd Hoffmann
parent 8ddab8dd3d
commit f00ff136ee
5 changed files with 148 additions and 0 deletions
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5
hw/usb/Kconfig
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@ -48,6 +48,11 @@ config USB_XHCI_NEC
depends on PCI
select USB_XHCI
config USB_XHCI_SYSBUS
bool
default y if USB_XHCI
select USB
config USB_MUSB
bool
select USB

109
hw/usb/hcd-xhci-sysbus.c Normal file
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@ -0,0 +1,109 @@
/*
* USB xHCI controller for system-bus interface
* Based on hcd-echi-sysbus.c
* SPDX-FileCopyrightText: 2020 Xilinx
* SPDX-FileContributor: Author: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include "qemu/osdep.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "trace.h"
#include "qapi/error.h"
#include "hcd-xhci-sysbus.h"
#include "hw/irq.h"
static void xhci_sysbus_intr_raise(XHCIState *xhci, int n, bool level)
{
XHCISysbusState *s = container_of(xhci, XHCISysbusState, xhci);
qemu_set_irq(s->irq[n], level);
}
void xhci_sysbus_reset(DeviceState *dev)
{
XHCISysbusState *s = XHCI_SYSBUS(dev);
device_legacy_reset(DEVICE(&s->xhci));
}
static void xhci_sysbus_realize(DeviceState *dev, Error **errp)
{
XHCISysbusState *s = XHCI_SYSBUS(dev);
Error *err = NULL;
object_property_set_link(OBJECT(&s->xhci), "host", OBJECT(s), NULL);
object_property_set_bool(OBJECT(&s->xhci), "realized", true, &err);
if (err) {
error_propagate(errp, err);
return;
}
s->irq = g_new0(qemu_irq, s->xhci.numintrs);
qdev_init_gpio_out_named(dev, s->irq, SYSBUS_DEVICE_GPIO_IRQ,
s->xhci.numintrs);
if (s->xhci.dma_mr) {
s->xhci.as = g_malloc0(sizeof(AddressSpace));
address_space_init(s->xhci.as, s->xhci.dma_mr, NULL);
} else {
s->xhci.as = &address_space_memory;
}
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->xhci.mem);
}
static void xhci_sysbus_instance_init(Object *obj)
{
XHCISysbusState *s = XHCI_SYSBUS(obj);
object_initialize_child(obj, "xhci-core", &s->xhci, TYPE_XHCI);
qdev_alias_all_properties(DEVICE(&s->xhci), obj);
object_property_add_link(obj, "dma", TYPE_MEMORY_REGION,
(Object **)&s->xhci.dma_mr,
qdev_prop_allow_set_link_before_realize,
OBJ_PROP_LINK_STRONG);
s->xhci.intr_update = NULL;
s->xhci.intr_raise = xhci_sysbus_intr_raise;
}
static Property xhci_sysbus_props[] = {
DEFINE_PROP_UINT32("intrs", XHCISysbusState, xhci.numintrs, MAXINTRS),
DEFINE_PROP_UINT32("slots", XHCISysbusState, xhci.numslots, MAXSLOTS),
DEFINE_PROP_END_OF_LIST(),
};
static const VMStateDescription vmstate_xhci_sysbus = {
.name = "xhci-sysbus",
.version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_STRUCT(xhci, XHCISysbusState, 1, vmstate_xhci, XHCIState),
VMSTATE_END_OF_LIST()
}
};
static void xhci_sysbus_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = xhci_sysbus_reset;
dc->realize = xhci_sysbus_realize;
dc->vmsd = &vmstate_xhci_sysbus;
device_class_set_props(dc, xhci_sysbus_props);
}
static const TypeInfo xhci_sysbus_info = {
.name = TYPE_XHCI_SYSBUS,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(XHCISysbusState),
.class_init = xhci_sysbus_class_init,
.instance_init = xhci_sysbus_instance_init
};
static void xhci_sysbus_register_types(void)
{
type_register_static(&xhci_sysbus_info);
}
type_init(xhci_sysbus_register_types);

32
hw/usb/hcd-xhci-sysbus.h Normal file
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@ -0,0 +1,32 @@
/*
* USB xHCI controller for system-bus interface
*
* SPDX-FileCopyrightText: 2020 Xilinx
* SPDX-FileContributor: Author: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
* SPDX-sourceInfo: Based on hcd-echi-sysbus
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#ifndef HW_USB_HCD_XHCI_SYSBUS_H
#define HW_USB_HCD_XHCI_SYSBUS_H
#include "hw/usb.h"
#include "hcd-xhci.h"
#include "hw/sysbus.h"
#define TYPE_XHCI_SYSBUS "sysbus-xhci"
#define XHCI_SYSBUS(obj) \
OBJECT_CHECK(XHCISysbusState, (obj), TYPE_XHCI_SYSBUS)
typedef struct XHCISysbusState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
XHCIState xhci;
qemu_irq *irq;
} XHCISysbusState;
void xhci_sysbus_reset(DeviceState *dev);
#endif

1
hw/usb/hcd-xhci.h
View File

@ -189,6 +189,7 @@ typedef struct XHCIState {
USBBus bus;
MemoryRegion mem;
MemoryRegion *dma_mr;
AddressSpace *as;
MemoryRegion mem_cap;
MemoryRegion mem_oper;

1
hw/usb/meson.build
View File

@ -22,6 +22,7 @@ softmmu_ss.add(when: 'CONFIG_USB_EHCI_PCI', if_true: files('hcd-ehci-pci.c'))
softmmu_ss.add(when: 'CONFIG_USB_EHCI_SYSBUS', if_true: files('hcd-ehci.c', 'hcd-ehci-sysbus.c'))
softmmu_ss.add(when: 'CONFIG_USB_XHCI', if_true: files('hcd-xhci.c'))
softmmu_ss.add(when: 'CONFIG_USB_XHCI_PCI', if_true: files('hcd-xhci-pci.c'))
softmmu_ss.add(when: 'CONFIG_USB_XHCI_SYSBUS', if_true: files('hcd-xhci-sysbus.c'))
softmmu_ss.add(when: 'CONFIG_USB_XHCI_NEC', if_true: files('hcd-xhci-nec.c'))
softmmu_ss.add(when: 'CONFIG_USB_MUSB', if_true: files('hcd-musb.c'))
softmmu_ss.add(when: 'CONFIG_USB_DWC2', if_true: files('hcd-dwc2.c'))