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igb: Clear-on-read ICR when ICR.INTA is set

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For GPIE.NSICR, Section 7.3.2.1.2 says:
> ICR bits are cleared on register read. If GPIE.NSICR = 0b, then the
> clear on read occurs only if no bit is set in the IMS or at least one
> bit is set in the IMS and there is a true interrupt as reflected in
> ICR.INTA.

e1000e does similar though it checks for CTRL_EXT.IAME, which does not
exist on igb.

Suggested-by: Sriram Yagnaraman <sriram.yagnaraman@est.tech>
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
This commit is contained in:
Akihiko Odaki 2023-05-23 11:43:36 +09:00 committed by Jason Wang
parent 5844562b17
commit efb1fd7a73
1 changed files with 2 additions and 0 deletions
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2
hw/net/igb_core.c
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@ -2598,6 +2598,8 @@ igb_mac_icr_read(IGBCore *core, int index)
} else if (core->mac[IMS] == 0) {
trace_e1000e_irq_icr_clear_zero_ims();
igb_lower_interrupts(core, ICR, 0xffffffff);
} else if (core->mac[ICR] & E1000_ICR_INT_ASSERTED) {
igb_lower_interrupts(core, ICR, 0xffffffff);
} else if (!msix_enabled(core->owner)) {
trace_e1000e_irq_icr_clear_nonmsix_icr_read();
igb_lower_interrupts(core, ICR, 0xffffffff);