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hw/riscv: opentitan: Update to the latest build

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Update the OpenTitan machine model to match the latest OpenTitan FPGA
design.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 18b1b681b0f8dd2461e819d1217bf0b530812680.1634524691.git.alistair.francis@wdc.com
This commit is contained in:
Alistair Francis 2021-10-18 12:38:39 +10:00
parent b550f89457
commit ef63100648
2 changed files with 20 additions and 8 deletions
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22
hw/riscv/opentitan.c
View File

@ -46,19 +46,19 @@ static const MemMapEntry ibex_memmap[] = {
[IBEX_DEV_PINMUX] = { 0x40460000, 0x1000 },
[IBEX_DEV_PADCTRL] = { 0x40470000, 0x1000 },
[IBEX_DEV_FLASH_CTRL] = { 0x41000000, 0x1000 },
[IBEX_DEV_PLIC] = { 0x41010000, 0x1000 },
[IBEX_DEV_AES] = { 0x41100000, 0x1000 },
[IBEX_DEV_HMAC] = { 0x41110000, 0x1000 },
[IBEX_DEV_KMAC] = { 0x41120000, 0x1000 },
[IBEX_DEV_KEYMGR] = { 0x41130000, 0x1000 },
[IBEX_DEV_OTBN] = { 0x41130000, 0x10000 },
[IBEX_DEV_KEYMGR] = { 0x41140000, 0x1000 },
[IBEX_DEV_CSRNG] = { 0x41150000, 0x1000 },
[IBEX_DEV_ENTROPY] = { 0x41160000, 0x1000 },
[IBEX_DEV_EDNO] = { 0x41170000, 0x1000 },
[IBEX_DEV_EDN1] = { 0x41180000, 0x1000 },
[IBEX_DEV_ALERT_HANDLER] = { 0x411b0000, 0x1000 },
[IBEX_DEV_NMI_GEN] = { 0x411c0000, 0x1000 },
[IBEX_DEV_OTBN] = { 0x411d0000, 0x10000 },
[IBEX_DEV_PERI] = { 0x411f0000, 0x10000 },
[IBEX_DEV_PLIC] = { 0x48000000, 0x4005000 },
[IBEX_DEV_FLASH_VIRTUAL] = { 0x80000000, 0x80000 },
};
@ -105,7 +105,7 @@ static void lowrisc_ibex_soc_init(Object *obj)
object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
object_initialize_child(obj, "plic", &s->plic, TYPE_IBEX_PLIC);
object_initialize_child(obj, "plic", &s->plic, TYPE_SIFIVE_PLIC);
object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART);
@ -145,6 +145,18 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
&s->flash_alias);
/* PLIC */
qdev_prop_set_string(DEVICE(&s->plic), "hart-config", "M");
qdev_prop_set_uint32(DEVICE(&s->plic), "hartid-base", 0);
qdev_prop_set_uint32(DEVICE(&s->plic), "num-sources", 180);
qdev_prop_set_uint32(DEVICE(&s->plic), "num-priorities", 3);
qdev_prop_set_uint32(DEVICE(&s->plic), "priority-base", 0x00);
qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000);
qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000);
qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 0x18);
qdev_prop_set_uint32(DEVICE(&s->plic), "context-base", 0x200004);
qdev_prop_set_uint32(DEVICE(&s->plic), "context-stride", 4);
qdev_prop_set_uint32(DEVICE(&s->plic), "aperture-size", memmap[IBEX_DEV_PLIC].size);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->plic), errp)) {
return;
}
@ -153,7 +165,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
for (i = 0; i < ms->smp.cpus; i++) {
CPUState *cpu = qemu_get_cpu(i);
qdev_connect_gpio_out(DEVICE(&s->plic), i,
qdev_connect_gpio_out(DEVICE(&s->plic), ms->smp.cpus + i,
qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
}

6
include/hw/riscv/opentitan.h
View File

@ -20,7 +20,7 @@
#define HW_OPENTITAN_H
#include "hw/riscv/riscv_hart.h"
#include "hw/intc/ibex_plic.h"
#include "hw/intc/sifive_plic.h"
#include "hw/char/ibex_uart.h"
#include "hw/timer/ibex_timer.h"
#include "qom/object.h"
@ -34,7 +34,7 @@ struct LowRISCIbexSoCState {
/*< public >*/
RISCVHartArrayState cpus;
IbexPlicState plic;
SiFivePLICState plic;
IbexUartState uart;
IbexTimerState timer;
@ -87,7 +87,7 @@ enum {
};
enum {
IBEX_TIMER_TIMEREXPIRED0_0 = 125,
IBEX_TIMER_TIMEREXPIRED0_0 = 126,
IBEX_UART0_RX_PARITY_ERR_IRQ = 8,
IBEX_UART0_RX_TIMEOUT_IRQ = 7,
IBEX_UART0_RX_BREAK_ERR_IRQ = 6,