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arm/gicv3: update virtual irq state after IAR register read

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The IAR0/IAR1 register is used to acknowledge an interrupt - a read of the
register activates the highest priority pending interrupt and provides its
interrupt ID. Activating an interrupt can change the CPU's virtual interrupt
state - this change makes sure the virtual irq state is updated.

Signed-off-by: Jeff Kubascik <jeff.kubascik@dornerworks.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200113154607.97032-1-jeff.kubascik@dornerworks.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Jeff Kubascik 2020-01-17 14:09:31 +00:00 committed by Peter Maydell
parent 855532912b
commit ef1255212a
1 changed files with 3 additions and 0 deletions
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hw/intc/arm_gicv3_cpuif.c
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@ -664,6 +664,9 @@ static uint64_t icv_iar_read(CPUARMState *env, const ARMCPRegInfo *ri)
trace_gicv3_icv_iar_read(ri->crm == 8 ? 0 : 1, trace_gicv3_icv_iar_read(ri->crm == 8 ? 0 : 1,
gicv3_redist_affid(cs), intid); gicv3_redist_affid(cs), intid);
gicv3_cpuif_virt_update(cs);
return intid; return intid;
} }