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target/loongarch: Support LoongArch32 DMW

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LA32 uses a different encoding for CSR.DMW and a new direct mapping
mechanism.

Signed-off-by: Jiajie Chen <c@jia.je>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-ID: <20230822032724.1353391-3-gaosong@loongson.cn>
Message-Id: <20230822071405.35386-3-philmd@linaro.org>
This commit is contained in:
Jiajie Chen 2023-08-22 09:13:48 +02:00 committed by Song Gao
parent e70bb6fb9a
commit eece576409
No known key found for this signature in database
GPG Key ID: 40A2FFF239263EDF
2 changed files with 26 additions and 7 deletions
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7
target/loongarch/cpu-csr.h
View File

@ -188,10 +188,9 @@ FIELD(CSR_DMW, PLV1, 1, 1)
FIELD(CSR_DMW, PLV2, 2, 1) FIELD(CSR_DMW, PLV2, 2, 1)
FIELD(CSR_DMW, PLV3, 3, 1) FIELD(CSR_DMW, PLV3, 3, 1)
FIELD(CSR_DMW, MAT, 4, 2) FIELD(CSR_DMW, MAT, 4, 2)
FIELD(CSR_DMW, VSEG, 60, 4) FIELD(CSR_DMW_32, PSEG, 25, 3)
FIELD(CSR_DMW_32, VSEG, 29, 3)
#define dmw_va2pa(va) \ FIELD(CSR_DMW_64, VSEG, 60, 4)
(va & MAKE_64BIT_MASK(0, TARGET_VIRT_ADDR_SPACE_BITS))
/* Debug CSRs */ /* Debug CSRs */
#define LOONGARCH_CSR_DBG 0x500 /* debug config */ #define LOONGARCH_CSR_DBG 0x500 /* debug config */

26
target/loongarch/tlb_helper.c
View File

@ -173,6 +173,18 @@ static int loongarch_map_address(CPULoongArchState *env, hwaddr *physical,
return TLBRET_NOMATCH; return TLBRET_NOMATCH;
} }
static hwaddr dmw_va2pa(CPULoongArchState *env, target_ulong va,
target_ulong dmw)
{
if (is_la64(env)) {
return va & TARGET_VIRT_MASK;
} else {
uint32_t pseg = FIELD_EX32(dmw, CSR_DMW_32, PSEG);
return (va & MAKE_64BIT_MASK(0, R_CSR_DMW_32_VSEG_SHIFT)) | \
(pseg << R_CSR_DMW_32_VSEG_SHIFT);
}
}
static int get_physical_address(CPULoongArchState *env, hwaddr *physical, static int get_physical_address(CPULoongArchState *env, hwaddr *physical,
int *prot, target_ulong address, int *prot, target_ulong address,
MMUAccessType access_type, int mmu_idx) MMUAccessType access_type, int mmu_idx)
@ -192,12 +204,20 @@ static int get_physical_address(CPULoongArchState *env, hwaddr *physical,
} }
plv = kernel_mode | (user_mode << R_CSR_DMW_PLV3_SHIFT); plv = kernel_mode | (user_mode << R_CSR_DMW_PLV3_SHIFT);
base_v = address >> R_CSR_DMW_VSEG_SHIFT; if (is_la64(env)) {
base_v = address >> R_CSR_DMW_64_VSEG_SHIFT;
} else {
base_v = address >> R_CSR_DMW_32_VSEG_SHIFT;
}
/* Check direct map window */ /* Check direct map window */
for (int i = 0; i < 4; i++) { for (int i = 0; i < 4; i++) {
base_c = FIELD_EX64(env->CSR_DMW[i], CSR_DMW, VSEG); if (is_la64(env)) {
base_c = FIELD_EX64(env->CSR_DMW[i], CSR_DMW_64, VSEG);
} else {
base_c = FIELD_EX64(env->CSR_DMW[i], CSR_DMW_32, VSEG);
}
if ((plv & env->CSR_DMW[i]) && (base_c == base_v)) { if ((plv & env->CSR_DMW[i]) && (base_c == base_v)) {
*physical = dmw_va2pa(address); *physical = dmw_va2pa(env, address, env->CSR_DMW[i]);
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
return TLBRET_MATCH; return TLBRET_MATCH;
} }