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target/i386: Assert CODE64 for x86_64 user-only

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For x86_64 user-only, there is no way to leave 64-bit mode.

Without x86_64, there is no way to enter 64-bit mode.  There is
an existing macro to aid with that; simply place it in the right
place in the ifdef chain.

Since we're adding an accessor macro, pull the value directly out
of flags when we're not assuming a constant.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20210514151342.384376-13-richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2021-05-14 10:13:04 -05:00
parent b40a47a17f
commit eec7d0f838
1 changed files with 8 additions and 4 deletions
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12
target/i386/tcg/translate.c
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@ -41,11 +41,9 @@
#define PREFIX_VEX 0x20 #define PREFIX_VEX 0x20
#ifdef TARGET_X86_64 #ifdef TARGET_X86_64
#define CODE64(s) ((s)->code64)
#define REX_X(s) ((s)->rex_x) #define REX_X(s) ((s)->rex_x)
#define REX_B(s) ((s)->rex_b) #define REX_B(s) ((s)->rex_b)
#else #else
#define CODE64(s) 0
#define REX_X(s) 0 #define REX_X(s) 0
#define REX_B(s) 0 #define REX_B(s) 0
#endif #endif
@ -102,7 +100,6 @@ typedef struct DisasContext {
#ifdef TARGET_X86_64 #ifdef TARGET_X86_64
int lma; /* long mode active */ int lma; /* long mode active */
int code64; /* 64 bit code segment */
int rex_x, rex_b; int rex_x, rex_b;
#endif #endif
int vex_l; /* vex vector length */ int vex_l; /* vex vector length */
@ -165,6 +162,13 @@ typedef struct DisasContext {
#define CODE32(S) (((S)->flags & HF_CS32_MASK) != 0) #define CODE32(S) (((S)->flags & HF_CS32_MASK) != 0)
#define SS32(S) (((S)->flags & HF_SS32_MASK) != 0) #define SS32(S) (((S)->flags & HF_SS32_MASK) != 0)
#endif #endif
#if !defined(TARGET_X86_64)
#define CODE64(S) false
#elif defined(CONFIG_USER_ONLY)
#define CODE64(S) true
#else
#define CODE64(S) (((S)->flags & HF_CS64_MASK) != 0)
#endif
static void gen_eob(DisasContext *s); static void gen_eob(DisasContext *s);
static void gen_jr(DisasContext *s, TCGv dest); static void gen_jr(DisasContext *s, TCGv dest);
@ -8497,6 +8501,7 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
g_assert(IOPL(dc) == iopl); g_assert(IOPL(dc) == iopl);
g_assert(VM86(dc) == ((flags & HF_VM_MASK) != 0)); g_assert(VM86(dc) == ((flags & HF_VM_MASK) != 0));
g_assert(CODE32(dc) == ((flags & HF_CS32_MASK) != 0)); g_assert(CODE32(dc) == ((flags & HF_CS32_MASK) != 0));
g_assert(CODE64(dc) == ((flags & HF_CS64_MASK) != 0));
g_assert(SS32(dc) == ((flags & HF_SS32_MASK) != 0)); g_assert(SS32(dc) == ((flags & HF_SS32_MASK) != 0));
dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1; dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1;
@ -8518,7 +8523,6 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
dc->cpuid_xsave_features = env->features[FEAT_XSAVE]; dc->cpuid_xsave_features = env->features[FEAT_XSAVE];
#ifdef TARGET_X86_64 #ifdef TARGET_X86_64
dc->lma = (flags >> HF_LMA_SHIFT) & 1; dc->lma = (flags >> HF_LMA_SHIFT) & 1;
dc->code64 = (flags >> HF_CS64_SHIFT) & 1;
#endif #endif
dc->jmp_opt = !(dc->tf || dc->base.singlestep_enabled || dc->jmp_opt = !(dc->tf || dc->base.singlestep_enabled ||
(flags & HF_INHIBIT_IRQ_MASK)); (flags & HF_INHIBIT_IRQ_MASK));