target/arm/ptw.c: Account for FEAT_RME when applying {N}SW, SA bits
In get_phys_addr_twostage() the code that applies the effects of VSTCR.{SA,SW} and VTCR.{NSA,NSW} only updates result->f.attrs.secure. Now we also have f.attrs.space for FEAT_RME, we need to keep the two in sync. These bits only have an effect for Secure space translations, not for Root, so use the input in_space field to determine whether to apply them rather than the input is_secure. This doesn't actually make a difference because Root translations are never two-stage, but it's a little clearer. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230710152130.3928330-4-peter.maydell@linaro.org
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@ -3118,6 +3118,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
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hwaddr ipa;
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int s1_prot, s1_lgpgsz;
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bool is_secure = ptw->in_secure;
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ARMSecuritySpace in_space = ptw->in_space;
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bool ret, ipa_secure;
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ARMCacheAttrs cacheattrs1;
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ARMSecuritySpace ipa_space;
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@ -3200,11 +3201,13 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
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* Check if IPA translates to secure or non-secure PA space.
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* Note that VSTCR overrides VTCR and {N}SW overrides {N}SA.
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*/
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result->f.attrs.secure =
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(is_secure
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&& !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW))
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&& (ipa_secure
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|| !(env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW))));
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if (in_space == ARMSS_Secure) {
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result->f.attrs.secure =
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!(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW))
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&& (ipa_secure
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|| !(env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW)));
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result->f.attrs.space = arm_secure_to_space(result->f.attrs.secure);
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}
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return false;
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}
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