Initial support for SS-2 (Sun4c)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3870 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
blueswir1
parent
7d85892b9b
commit
ee76f82edb
@ -486,7 +486,7 @@ VL_OBJS+= cirrus_vga.o parallel.o ptimer.o
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else
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VL_OBJS+= sun4m.o tcx.o pcnet.o iommu.o m48t59.o slavio_intctl.o
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VL_OBJS+= slavio_timer.o slavio_serial.o slavio_misc.o fdc.o esp.o sparc32_dma.o
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VL_OBJS+= cs4231.o ptimer.o eccmemctl.o sbi.o
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VL_OBJS+= cs4231.o ptimer.o eccmemctl.o sbi.o sun4c_intctl.o
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endif
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endif
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ifeq ($(TARGET_BASE_ARCH), arm)
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@ -53,6 +53,7 @@ extern QEMUMachine r2d_machine;
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/* sun4m.c */
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extern QEMUMachine ss5_machine, ss10_machine, ss600mp_machine, ss20_machine;
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extern QEMUMachine ss2_machine;
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extern QEMUMachine ss1000_machine, ss2000_machine;
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/* sun4u.c */
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223
hw/sun4c_intctl.c
Normal file
223
hw/sun4c_intctl.c
Normal file
@ -0,0 +1,223 @@
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/*
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* QEMU Sparc Sun4c interrupt controller emulation
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*
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* Based on slavio_intctl, copyright (c) 2003-2005 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "sun4m.h"
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#include "console.h"
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//#define DEBUG_IRQ_COUNT
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//#define DEBUG_IRQ
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#ifdef DEBUG_IRQ
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#define DPRINTF(fmt, args...) \
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do { printf("IRQ: " fmt , ##args); } while (0)
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#else
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#define DPRINTF(fmt, args...)
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#endif
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/*
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* Registers of interrupt controller in sun4c.
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*
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*/
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#define MAX_PILS 16
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typedef struct Sun4c_INTCTLState {
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#ifdef DEBUG_IRQ_COUNT
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uint64_t irq_count;
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#endif
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qemu_irq *cpu_irqs;
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const uint32_t *intbit_to_level;
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uint32_t pil_out;
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uint8_t reg;
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uint8_t pending;
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} Sun4c_INTCTLState;
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#define INTCTL_MAXADDR 0
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#define INTCTL_SIZE (INTCTL_MAXADDR + 1)
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static void sun4c_check_interrupts(void *opaque);
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static uint32_t sun4c_intctl_mem_readb(void *opaque, target_phys_addr_t addr)
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{
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Sun4c_INTCTLState *s = opaque;
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uint32_t ret;
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ret = s->reg;
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DPRINTF("read reg 0x" TARGET_FMT_plx " = %x\n", addr, ret);
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return ret;
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}
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static void sun4c_intctl_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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Sun4c_INTCTLState *s = opaque;
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DPRINTF("write reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
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val &= 0xbf;
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s->reg = val;
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sun4c_check_interrupts(s);
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}
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static CPUReadMemoryFunc *sun4c_intctl_mem_read[3] = {
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sun4c_intctl_mem_readb,
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sun4c_intctl_mem_readb,
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sun4c_intctl_mem_readb,
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};
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static CPUWriteMemoryFunc *sun4c_intctl_mem_write[3] = {
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sun4c_intctl_mem_writeb,
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sun4c_intctl_mem_writeb,
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sun4c_intctl_mem_writeb,
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};
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void sun4c_pic_info(void *opaque)
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{
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Sun4c_INTCTLState *s = opaque;
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term_printf("master: pending 0x%2.2x, enabled 0x%2.2x\n", s->pending, s->reg);
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}
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void sun4c_irq_info(void *opaque)
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{
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#ifndef DEBUG_IRQ_COUNT
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term_printf("irq statistic code not compiled.\n");
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#else
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Sun4c_INTCTLState *s = opaque;
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int64_t count;
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term_printf("IRQ statistics:\n");
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count = s->irq_count[i];
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if (count > 0)
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term_printf("%2d: %" PRId64 "\n", i, count);
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#endif
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}
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static const uint32_t intbit_to_level[] = { 0, 1, 4, 6, 8, 10, 0, 14, };
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static void sun4c_check_interrupts(void *opaque)
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{
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Sun4c_INTCTLState *s = opaque;
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uint32_t pil_pending;
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unsigned int i;
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DPRINTF("pending %x disabled %x\n", pending, s->intregm_disabled);
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pil_pending = 0;
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if (s->pending && !(s->reg & 0x80000000)) {
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for (i = 0; i < 8; i++) {
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if (s->pending & (1 << i))
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pil_pending |= 1 << intbit_to_level[i];
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}
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}
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for (i = 0; i < MAX_PILS; i++) {
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if (pil_pending & (1 << i)) {
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if (!(s->pil_out & (1 << i)))
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qemu_irq_raise(s->cpu_irqs[i]);
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} else {
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if (s->pil_out & (1 << i))
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qemu_irq_lower(s->cpu_irqs[i]);
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}
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}
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s->pil_out = pil_pending;
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}
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/*
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* "irq" here is the bit number in the system interrupt register
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*/
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static void sun4c_set_irq(void *opaque, int irq, int level)
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{
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Sun4c_INTCTLState *s = opaque;
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uint32_t mask = 1 << irq;
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uint32_t pil = intbit_to_level[irq];
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DPRINTF("Set irq %d -> pil %d level %d\n", irq, pil,
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level);
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if (pil > 0) {
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if (level) {
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#ifdef DEBUG_IRQ_COUNT
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s->irq_count[pil]++;
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#endif
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s->pending |= mask;
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} else {
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s->pending &= ~mask;
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}
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sun4c_check_interrupts(s);
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}
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}
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static void sun4c_intctl_save(QEMUFile *f, void *opaque)
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{
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Sun4c_INTCTLState *s = opaque;
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qemu_put_8s(f, &s->reg);
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qemu_put_8s(f, &s->pending);
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}
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static int sun4c_intctl_load(QEMUFile *f, void *opaque, int version_id)
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{
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Sun4c_INTCTLState *s = opaque;
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if (version_id != 1)
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return -EINVAL;
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qemu_get_8s(f, &s->reg);
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qemu_get_8s(f, &s->pending);
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sun4c_check_interrupts(s);
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return 0;
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}
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static void sun4c_intctl_reset(void *opaque)
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{
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Sun4c_INTCTLState *s = opaque;
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s->reg = 1;
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s->pending = 0;
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sun4c_check_interrupts(s);
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}
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void *sun4c_intctl_init(target_phys_addr_t addr, qemu_irq **irq,
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qemu_irq *parent_irq)
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{
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int sun4c_intctl_io_memory;
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Sun4c_INTCTLState *s;
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s = qemu_mallocz(sizeof(Sun4c_INTCTLState));
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if (!s)
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return NULL;
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sun4c_intctl_io_memory = cpu_register_io_memory(0, sun4c_intctl_mem_read,
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sun4c_intctl_mem_write, s);
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cpu_register_physical_memory(addr, INTCTL_SIZE, sun4c_intctl_io_memory);
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s->cpu_irqs = parent_irq;
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register_savevm("sun4c_intctl", addr, 1, sun4c_intctl_save,
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sun4c_intctl_load, s);
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qemu_register_reset(sun4c_intctl_reset, s);
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*irq = qemu_allocate_irqs(sun4c_set_irq, s, 8);
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sun4c_intctl_reset(s);
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return s;
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}
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202
hw/sun4m.c
202
hw/sun4m.c
@ -1,5 +1,5 @@
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/*
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* QEMU Sun4m & Sun4d System Emulator
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* QEMU Sun4m & Sun4d & Sun4c System Emulator
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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@ -51,6 +51,13 @@
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* SPARCcenter 2000
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* SPARCserver 1000
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*
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* Sun4c architecture was used in the following machines:
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* SPARCstation 1/1+, SPARCserver 1/1+
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* SPARCstation SLC
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* SPARCstation IPC
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* SPARCstation ELC
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* SPARCstation IPX
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*
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* See for example: http://www.sunhelp.org/faq/sunref1.html
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*/
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@ -79,6 +86,7 @@ struct hwdef {
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target_phys_addr_t tcx_base, cs_base, power_base;
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target_phys_addr_t ecc_base;
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uint32_t ecc_version;
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target_phys_addr_t sun4c_intctl_base, sun4c_counter_base;
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long vram_size, nvram_size;
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// IRQ numbers are not PIL ones, but master interrupt controller register
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// bit numbers
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@ -521,6 +529,142 @@ static void sun4m_hw_init(const struct hwdef *hwdef, int RAM_size,
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ecc_init(hwdef->ecc_base, hwdef->ecc_version);
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}
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static void sun4c_hw_init(const struct hwdef *hwdef, int RAM_size,
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const char *boot_device,
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DisplayState *ds, const char *kernel_filename,
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const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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{
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CPUState *env;
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unsigned int i;
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void *iommu, *espdma, *ledma, *main_esp, *nvram;
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qemu_irq *cpu_irqs, *slavio_irq, *espdma_irq, *ledma_irq;
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qemu_irq *esp_reset, *le_reset;
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unsigned long prom_offset, kernel_size;
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int ret;
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char buf[1024];
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BlockDriverState *fd[MAX_FD];
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int index;
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/* init CPU */
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if (!cpu_model)
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cpu_model = hwdef->default_cpu_model;
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env = cpu_init(cpu_model);
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if (!env) {
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fprintf(stderr, "Unable to find Sparc CPU definition\n");
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exit(1);
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}
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cpu_sparc_set_id(env, 0);
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qemu_register_reset(main_cpu_reset, env);
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register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
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cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
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/* allocate RAM */
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if ((uint64_t)RAM_size > hwdef->max_mem) {
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fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n",
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(unsigned int)RAM_size / (1024 * 1024),
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(unsigned int)hwdef->max_mem / (1024 * 1024));
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exit(1);
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}
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cpu_register_physical_memory(0, RAM_size, 0);
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/* load boot prom */
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prom_offset = RAM_size + hwdef->vram_size;
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cpu_register_physical_memory(hwdef->slavio_base,
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(PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
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TARGET_PAGE_MASK,
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prom_offset | IO_MEM_ROM);
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if (bios_name == NULL)
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bios_name = PROM_FILENAME;
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snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
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ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
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if (ret < 0 || ret > PROM_SIZE_MAX)
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ret = load_image(buf, phys_ram_base + prom_offset);
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if (ret < 0 || ret > PROM_SIZE_MAX) {
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fprintf(stderr, "qemu: could not load prom '%s'\n",
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buf);
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exit(1);
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}
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prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
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/* set up devices */
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slavio_intctl = sun4c_intctl_init(hwdef->sun4c_intctl_base,
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&slavio_irq, cpu_irqs);
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iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version);
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espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
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iommu, &espdma_irq, &esp_reset);
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ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
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slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
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&le_reset);
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if (graphic_depth != 8 && graphic_depth != 24) {
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fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
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exit (1);
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}
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tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
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hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
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if (nd_table[0].model == NULL
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|| strcmp(nd_table[0].model, "lance") == 0) {
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lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
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} else if (strcmp(nd_table[0].model, "?") == 0) {
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fprintf(stderr, "qemu: Supported NICs: lance\n");
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exit (1);
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} else {
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fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
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exit (1);
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}
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nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
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hwdef->nvram_size, 8);
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slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
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nographic);
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// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
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// Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
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slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
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serial_hds[1], serial_hds[0]);
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if (hwdef->fd_base != (target_phys_addr_t)-1) {
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/* there is zero or one floppy drive */
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fd[1] = fd[0] = NULL;
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index = drive_get_index(IF_FLOPPY, 0, 0);
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if (index != -1)
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fd[0] = drives_table[index].bdrv;
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sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd);
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}
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if (drive_get_max_bus(IF_SCSI) > 0) {
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fprintf(stderr, "qemu: too many SCSI bus\n");
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exit(1);
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}
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main_esp = esp_init(hwdef->esp_base, espdma, *espdma_irq,
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esp_reset);
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for (i = 0; i < ESP_MAX_DEVS; i++) {
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index = drive_get_index(IF_SCSI, 0, i);
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if (index == -1)
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continue;
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esp_scsi_attach(main_esp, drives_table[index].bdrv, i);
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}
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kernel_size = sun4m_load_kernel(kernel_filename, kernel_cmdline,
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initrd_filename);
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nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
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boot_device, RAM_size, kernel_size, graphic_width,
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graphic_height, graphic_depth, hwdef->machine_id, "Sun4c");
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}
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static const struct hwdef hwdefs[] = {
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/* SS-5 */
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{
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@ -540,6 +684,8 @@ static const struct hwdef hwdefs[] = {
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.le_base = 0x78c00000,
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.power_base = 0x7a000000,
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.ecc_base = -1,
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.sun4c_intctl_base = -1,
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.sun4c_counter_base = -1,
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.vram_size = 0x00100000,
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.nvram_size = 0x2000,
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.esp_irq = 18,
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@ -579,6 +725,8 @@ static const struct hwdef hwdefs[] = {
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.power_base = 0xefa000000ULL,
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.ecc_base = 0xf00000000ULL,
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.ecc_version = 0x10000000, // version 0, implementation 1
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.sun4c_intctl_base = -1,
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.sun4c_counter_base = -1,
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.vram_size = 0x00100000,
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.nvram_size = 0x2000,
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.esp_irq = 18,
|
||||
@ -618,6 +766,8 @@ static const struct hwdef hwdefs[] = {
|
||||
.power_base = 0xefa000000ULL,
|
||||
.ecc_base = 0xf00000000ULL,
|
||||
.ecc_version = 0x00000000, // version 0, implementation 0
|
||||
.sun4c_intctl_base = -1,
|
||||
.sun4c_counter_base = -1,
|
||||
.vram_size = 0x00100000,
|
||||
.nvram_size = 0x2000,
|
||||
.esp_irq = 18,
|
||||
@ -657,6 +807,8 @@ static const struct hwdef hwdefs[] = {
|
||||
.power_base = 0xefa000000ULL,
|
||||
.ecc_base = 0xf00000000ULL,
|
||||
.ecc_version = 0x20000000, // version 0, implementation 2
|
||||
.sun4c_intctl_base = -1,
|
||||
.sun4c_counter_base = -1,
|
||||
.vram_size = 0x00100000,
|
||||
.nvram_size = 0x2000,
|
||||
.esp_irq = 18,
|
||||
@ -677,6 +829,39 @@ static const struct hwdef hwdefs[] = {
|
||||
.max_mem = 0xffffffff, // XXX actually first 62GB ok
|
||||
.default_cpu_model = "TI SuperSparc II",
|
||||
},
|
||||
/* SS-2 */
|
||||
{
|
||||
.iommu_base = 0xf8000000,
|
||||
.tcx_base = 0xfe000000,
|
||||
.cs_base = -1,
|
||||
.slavio_base = 0xf6000000,
|
||||
.ms_kb_base = 0xf0000000,
|
||||
.serial_base = 0xf1000000,
|
||||
.nvram_base = 0xf2000000,
|
||||
.fd_base = 0xf7200000,
|
||||
.counter_base = -1,
|
||||
.intctl_base = -1,
|
||||
.dma_base = 0xf8400000,
|
||||
.esp_base = 0xf8800000,
|
||||
.le_base = 0xf8c00000,
|
||||
.power_base = -1,
|
||||
.sun4c_intctl_base = 0xf5000000,
|
||||
.sun4c_counter_base = 0xf3000000,
|
||||
.vram_size = 0x00100000,
|
||||
.nvram_size = 0x2000, // XXX 0x800,
|
||||
.esp_irq = 2,
|
||||
.le_irq = 3,
|
||||
.clock_irq = 5,
|
||||
.clock1_irq = 7,
|
||||
.ms_kb_irq = 1,
|
||||
.ser_irq = 1,
|
||||
.fd_irq = 1,
|
||||
.me_irq = 1,
|
||||
.cs_irq = -1,
|
||||
.machine_id = 0x55,
|
||||
.max_mem = 0x10000000,
|
||||
.default_cpu_model = "Cypress CY7C601",
|
||||
},
|
||||
};
|
||||
|
||||
/* SPARCstation 5 hardware initialisation */
|
||||
@ -719,6 +904,16 @@ static void ss20_init(int RAM_size, int vga_ram_size,
|
||||
kernel_cmdline, initrd_filename, cpu_model);
|
||||
}
|
||||
|
||||
/* SPARCstation 2 hardware initialisation */
|
||||
static void ss2_init(int RAM_size, int vga_ram_size,
|
||||
const char *boot_device, DisplayState *ds,
|
||||
const char *kernel_filename, const char *kernel_cmdline,
|
||||
const char *initrd_filename, const char *cpu_model)
|
||||
{
|
||||
sun4c_hw_init(&hwdefs[4], RAM_size, boot_device, ds, kernel_filename,
|
||||
kernel_cmdline, initrd_filename, cpu_model);
|
||||
}
|
||||
|
||||
QEMUMachine ss5_machine = {
|
||||
"SS-5",
|
||||
"Sun4m platform, SPARCstation 5",
|
||||
@ -743,6 +938,11 @@ QEMUMachine ss20_machine = {
|
||||
ss20_init,
|
||||
};
|
||||
|
||||
QEMUMachine ss2_machine = {
|
||||
"SS-2",
|
||||
"Sun4c platform, SPARCstation 2",
|
||||
ss2_init,
|
||||
};
|
||||
|
||||
static const struct sun4d_hwdef sun4d_hwdefs[] = {
|
||||
/* SS-1000 */
|
||||
|
||||
@ -38,6 +38,10 @@ void slavio_irq_info(void *opaque);
|
||||
void *sbi_init(target_phys_addr_t addr, qemu_irq **irq, qemu_irq **cpu_irq,
|
||||
qemu_irq **parent_irq);
|
||||
|
||||
/* sun4c_intctl.c */
|
||||
void *sun4c_intctl_init(target_phys_addr_t addr, qemu_irq **irq,
|
||||
qemu_irq *parent_irq);
|
||||
|
||||
/* slavio_timer.c */
|
||||
void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
|
||||
qemu_irq *cpu_irqs, unsigned int num_cpus);
|
||||
|
||||
@ -74,7 +74,7 @@ For system emulation, the following hardware targets are supported:
|
||||
@item PREP (PowerPC processor)
|
||||
@item G3 BW PowerMac (PowerPC processor)
|
||||
@item Mac99 PowerMac (PowerPC processor, in progress)
|
||||
@item Sun4m/Sun4d (32-bit Sparc processor)
|
||||
@item Sun4m/Sun4c/Sun4d (32-bit Sparc processor)
|
||||
@item Sun4u (64-bit Sparc processor, in progress)
|
||||
@item Malta board (32-bit and 64-bit MIPS processors)
|
||||
@item ARM Integrator/CP (ARM)
|
||||
@ -2026,10 +2026,11 @@ More information is available at
|
||||
@section Sparc32 System emulator
|
||||
|
||||
Use the executable @file{qemu-system-sparc} to simulate a SPARCstation
|
||||
5, SPARCstation 10, SPARCstation 20, SPARCserver 600MP (sun4m architecture),
|
||||
SPARCserver 1000, or SPARCcenter 2000 (sun4d architecture). The
|
||||
emulation is somewhat complete. SMP up to 16 CPUs is supported, but
|
||||
Linux limits the number of usable CPUs to 4.
|
||||
5, SPARCstation 10, SPARCstation 20, SPARCserver 600MP (sun4m
|
||||
architecture), SPARCstation 2 (sun4c architecture), SPARCserver 1000,
|
||||
or SPARCcenter 2000 (sun4d architecture). The emulation is somewhat
|
||||
complete. SMP up to 16 CPUs is supported, but Linux limits the number
|
||||
of usable CPUs to 4.
|
||||
|
||||
QEMU emulates the following sun4m/sun4d peripherals:
|
||||
|
||||
@ -2086,7 +2087,7 @@ qemu-system-sparc -prom-env 'auto-boot?=false' \
|
||||
-prom-env 'boot-device=sd(0,2,0):d' -prom-env 'boot-args=linux single'
|
||||
@end example
|
||||
|
||||
@item -M [SS-5|SS-10|SS-20|SS-600MP|SS-1000|SS-2000]
|
||||
@item -M [SS-5|SS-10|SS-20|SS-600MP|SS-2|SS-1000|SS-2000]
|
||||
|
||||
Set the emulated machine type. Default is SS-5.
|
||||
|
||||
|
||||
1
vl.c
1
vl.c
@ -7892,6 +7892,7 @@ static void register_machines(void)
|
||||
qemu_register_machine(&ss10_machine);
|
||||
qemu_register_machine(&ss600mp_machine);
|
||||
qemu_register_machine(&ss20_machine);
|
||||
qemu_register_machine(&ss2_machine);
|
||||
qemu_register_machine(&ss1000_machine);
|
||||
qemu_register_machine(&ss2000_machine);
|
||||
#endif
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user