From eddf68a6ac4b5ca6eb1efbb69e50d04878a87aa5 Mon Sep 17 00:00:00 2001 From: j_mayer Date: Thu, 5 Apr 2007 07:22:49 +0000 Subject: [PATCH] Integrate Alpha target in Qemu core. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2601 c046a42c-6fe2-441c-8c8c-71466251a162 --- cpu-all.h | 7 +++++ cpu-exec.c | 71 +++++++++++++++++++++++++++++++++++++++++++++++- dis-asm.h | 2 ++ disas.c | 3 ++ exec-all.h | 2 ++ softmmu_header.h | 4 +++ translate-all.c | 2 ++ vl.c | 2 ++ 8 files changed, 92 insertions(+), 1 deletion(-) diff --git a/cpu-all.h b/cpu-all.h index 08d42188a8..d2382857a5 100644 --- a/cpu-all.h +++ b/cpu-all.h @@ -748,6 +748,13 @@ void page_unprotect_range(target_ulong data, target_ulong data_size); #define cpu_gen_code cpu_sh4_gen_code #define cpu_signal_handler cpu_sh4_signal_handler +#elif defined(TARGET_ALPHA) +#define CPUState CPUAlphaState +#define cpu_init cpu_alpha_init +#define cpu_exec cpu_alpha_exec +#define cpu_gen_code cpu_alpha_gen_code +#define cpu_signal_handler cpu_alpha_signal_handler + #else #error unsupported target CPU diff --git a/cpu-exec.c b/cpu-exec.c index 4916b1af6d..0eabacd643 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -40,7 +40,8 @@ int tb_invalidated_flag; //#define DEBUG_EXEC //#define DEBUG_SIGNAL -#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_M68K) +#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_M68K) || \ + defined(TARGET_ALPHA) /* XXX: unify with i386 target */ void cpu_loop_exit(void) { @@ -202,6 +203,10 @@ static inline TranslationBlock *tb_find_fast(void) flags = env->sr & (SR_MD | SR_RB); cs_base = 0; /* XXXXX */ pc = env->pc; +#elif defined(TARGET_ALPHA) + flags = env->ps; + cs_base = 0; + pc = env->pc; #else #error unsupported CPU #endif @@ -291,6 +296,14 @@ int cpu_exec(CPUState *env1) return EXCP_HALTED; } } +#elif defined(TARGET_ALPHA) + if (env1->halted) { + if (env1->interrupt_request & CPU_INTERRUPT_HARD) { + env1->halted = 0; + } else { + return EXCP_HALTED; + } + } #endif cpu_single_env = env1; @@ -324,6 +337,8 @@ int cpu_exec(CPUState *env1) #elif defined(TARGET_MIPS) #elif defined(TARGET_SH4) /* XXXXX */ +#elif defined(TARGET_ALPHA) + env_to_regs(); #else #error unsupported target CPU #endif @@ -372,6 +387,8 @@ int cpu_exec(CPUState *env1) do_interrupt(env); #elif defined(TARGET_SH4) do_interrupt(env); +#elif defined(TARGET_ALPHA) + do_interrupt(env); #endif } env->exception_index = -1; @@ -518,6 +535,10 @@ int cpu_exec(CPUState *env1) } #elif defined(TARGET_SH4) /* XXXXX */ +#elif defined(TARGET_ALPHA) + if (interrupt_request & CPU_INTERRUPT_HARD) { + do_interrupt(env); + } #endif /* Don't use the cached interupt_request value, do_interrupt may have updated the EXITTB flag. */ @@ -586,6 +607,8 @@ int cpu_exec(CPUState *env1) cpu_dump_state(env, logfile, fprintf, 0); #elif defined(TARGET_SH4) cpu_dump_state(env, logfile, fprintf, 0); +#elif defined(TARGET_ALPHA) + cpu_dump_state(env, logfile, fprintf, 0); #else #error unsupported target CPU #endif @@ -778,6 +801,7 @@ int cpu_exec(CPUState *env1) | env->cc_dest | (env->cc_x << 4); #elif defined(TARGET_MIPS) #elif defined(TARGET_SH4) +#elif defined(TARGET_ALPHA) /* XXXXX */ #else #error unsupported target CPU @@ -1164,6 +1188,51 @@ static inline int handle_cpu_signal(unsigned long pc, unsigned long address, /* never comes here */ return 1; } + +#elif defined (TARGET_ALPHA) +static inline int handle_cpu_signal(unsigned long pc, unsigned long address, + int is_write, sigset_t *old_set, + void *puc) +{ + TranslationBlock *tb; + int ret; + + if (cpu_single_env) + env = cpu_single_env; /* XXX: find a correct solution for multithread */ +#if defined(DEBUG_SIGNAL) + printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", + pc, address, is_write, *(unsigned long *)old_set); +#endif + /* XXX: locking issue */ + if (is_write && page_unprotect(h2g(address), pc, puc)) { + return 1; + } + + /* see if it is an MMU fault */ + ret = cpu_alpha_handle_mmu_fault(env, address, is_write, 1, 0); + if (ret < 0) + return 0; /* not an MMU fault */ + if (ret == 0) + return 1; /* the MMU fault was handled without causing real CPU fault */ + + /* now we have a real cpu fault */ + tb = tb_find_pc(pc); + if (tb) { + /* the PC is inside the translated code. It means that we have + a virtual CPU fault */ + cpu_restore_state(tb, env, pc, puc); + } +#if 0 + printf("PF exception: NIP=0x%08x error=0x%x %p\n", + env->nip, env->error_code, tb); +#endif + /* we restore the process signal mask as the sigreturn should + do it (XXX: use sigsetjmp) */ + sigprocmask(SIG_SETMASK, old_set, NULL); + cpu_loop_exit(); + /* never comes here */ + return 1; +} #else #error unsupported target CPU #endif diff --git a/dis-asm.h b/dis-asm.h index 73b4380b78..2b2f1d1dec 100644 --- a/dis-asm.h +++ b/dis-asm.h @@ -181,6 +181,7 @@ enum bfd_architecture #define bfd_mach_sh4al_dsp 0x4d #define bfd_mach_sh5 0x50 bfd_arch_alpha, /* Dec Alpha */ +#define bfd_mach_alpha 1 bfd_arch_arm, /* Advanced Risc Machines ARM */ #define bfd_mach_arm_2 1 #define bfd_mach_arm_2a 2 @@ -377,6 +378,7 @@ extern int print_insn_d10v PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_v850 PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_tic30 PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_ppc PARAMS ((bfd_vma, disassemble_info*)); +extern int print_insn_alpha PARAMS ((bfd_vma, disassemble_info*)); #if 0 /* Fetch the disassembler for a given BFD, if that support is available. */ diff --git a/disas.c b/disas.c index 2979927984..c583c1d4d1 100644 --- a/disas.c +++ b/disas.c @@ -197,6 +197,9 @@ void target_disas(FILE *out, target_ulong code, target_ulong size, int flags) #elif defined(TARGET_SH4) disasm_info.mach = bfd_mach_sh4; print_insn = print_insn_sh; +#elif defined(TARGET_ALPHA) + disasm_info.mach = bfd_mach_alpha; + print_insn = print_insn_alpha; #else fprintf(out, "0x" TARGET_FMT_lx ": Asm output not supported on this arch\n", code); diff --git a/exec-all.h b/exec-all.h index 73b85436c0..cb8936a69b 100644 --- a/exec-all.h +++ b/exec-all.h @@ -572,6 +572,8 @@ static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr) is_user = ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR); #elif defined (TARGET_SH4) is_user = ((env->sr & SR_MD) == 0); +#elif defined (TARGET_ALPHA) + is_user = ((env->ps >> 3) & 3); #else #error unimplemented CPU #endif diff --git a/softmmu_header.h b/softmmu_header.h index d5b3debc74..8c6cf74adb 100644 --- a/softmmu_header.h +++ b/softmmu_header.h @@ -63,6 +63,8 @@ #define CPU_MEM_INDEX ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR) #elif defined (TARGET_SH4) #define CPU_MEM_INDEX ((env->sr & SR_MD) == 0) +#elif defined (TARGET_ALPHA) +#define CPU_MEM_INDEX ((env->ps >> 3) & 3) #else #error unsupported CPU #endif @@ -82,6 +84,8 @@ #define CPU_MEM_INDEX ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR) #elif defined (TARGET_SH4) #define CPU_MEM_INDEX ((env->sr & SR_MD) == 0) +#elif defined (TARGET_ALPHA) +#define CPU_MEM_INDEX ((env->ps >> 3) & 3) #else #error unsupported CPU #endif diff --git a/translate-all.c b/translate-all.c index 43365478bd..491b3b3d33 100644 --- a/translate-all.c +++ b/translate-all.c @@ -308,6 +308,8 @@ int cpu_restore_state(TranslationBlock *tb, env->PC = gen_opc_pc[j]; env->hflags &= ~MIPS_HFLAG_BMASK; env->hflags |= gen_opc_hflags[j]; +#elif defined(TARGET_ALPHA) + env->pc = gen_opc_pc[j]; #endif return 0; } diff --git a/vl.c b/vl.c index 487c4a8d9a..355f7ff820 100644 --- a/vl.c +++ b/vl.c @@ -6707,6 +6707,8 @@ void register_machines(void) qemu_register_machine(&realview_machine); #elif defined(TARGET_SH4) qemu_register_machine(&shix_machine); +#elif defined(TARGET_ALPHA) + /* XXX: TODO */ #else #error unsupported CPU #endif