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target/arm: Implement SVE2 complex integer add

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-19-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2021-05-24 18:02:44 -07:00 committed by Peter Maydell
parent cb9c33b817
commit ed4a638726
4 changed files with 92 additions and 0 deletions
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10
target/arm/helper-sve.h
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@ -2392,3 +2392,13 @@ DEF_HELPER_FLAGS_4(sve2_bgrp_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve2_bgrp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve2_bgrp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve2_bgrp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve2_cadd_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve2_cadd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve2_cadd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve2_cadd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve2_sqcadd_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve2_sqcadd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve2_sqcadd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve2_sqcadd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)

9
target/arm/sve.decode
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@ -1226,3 +1226,12 @@ EORTB 01000101 .. 0 ..... 10010 1 ..... ..... @rd_rn_rm
BEXT 01000101 .. 0 ..... 1011 00 ..... ..... @rd_rn_rm
BDEP 01000101 .. 0 ..... 1011 01 ..... ..... @rd_rn_rm
BGRP 01000101 .. 0 ..... 1011 10 ..... ..... @rd_rn_rm
#### SVE2 Accumulate
## SVE2 complex integer add
CADD_rot90 01000101 .. 00000 0 11011 0 ..... ..... @rdn_rm
CADD_rot270 01000101 .. 00000 0 11011 1 ..... ..... @rdn_rm
SQCADD_rot90 01000101 .. 00000 1 11011 0 ..... ..... @rdn_rm
SQCADD_rot270 01000101 .. 00000 1 11011 1 ..... ..... @rdn_rm

42
target/arm/sve_helper.c
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@ -1319,6 +1319,48 @@ DO_BITPERM(sve2_bgrp_d, uint64_t, bitgroup)
#undef DO_BITPERM
#define DO_CADD(NAME, TYPE, H, ADD_OP, SUB_OP) \
void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \
{ \
intptr_t i, opr_sz = simd_oprsz(desc); \
int sub_r = simd_data(desc); \
if (sub_r) { \
for (i = 0; i < opr_sz; i += 2 * sizeof(TYPE)) { \
TYPE acc_r = *(TYPE *)(vn + H(i)); \
TYPE acc_i = *(TYPE *)(vn + H(i + sizeof(TYPE))); \
TYPE el2_r = *(TYPE *)(vm + H(i)); \
TYPE el2_i = *(TYPE *)(vm + H(i + sizeof(TYPE))); \
acc_r = ADD_OP(acc_r, el2_i); \
acc_i = SUB_OP(acc_i, el2_r); \
*(TYPE *)(vd + H(i)) = acc_r; \
*(TYPE *)(vd + H(i + sizeof(TYPE))) = acc_i; \
} \
} else { \
for (i = 0; i < opr_sz; i += 2 * sizeof(TYPE)) { \
TYPE acc_r = *(TYPE *)(vn + H(i)); \
TYPE acc_i = *(TYPE *)(vn + H(i + sizeof(TYPE))); \
TYPE el2_r = *(TYPE *)(vm + H(i)); \
TYPE el2_i = *(TYPE *)(vm + H(i + sizeof(TYPE))); \
acc_r = SUB_OP(acc_r, el2_i); \
acc_i = ADD_OP(acc_i, el2_r); \
*(TYPE *)(vd + H(i)) = acc_r; \
*(TYPE *)(vd + H(i + sizeof(TYPE))) = acc_i; \
} \
} \
}
DO_CADD(sve2_cadd_b, int8_t, H1, DO_ADD, DO_SUB)
DO_CADD(sve2_cadd_h, int16_t, H1_2, DO_ADD, DO_SUB)
DO_CADD(sve2_cadd_s, int32_t, H1_4, DO_ADD, DO_SUB)
DO_CADD(sve2_cadd_d, int64_t, , DO_ADD, DO_SUB)
DO_CADD(sve2_sqcadd_b, int8_t, H1, DO_SQADD_B, DO_SQSUB_B)
DO_CADD(sve2_sqcadd_h, int16_t, H1_2, DO_SQADD_H, DO_SQSUB_H)
DO_CADD(sve2_sqcadd_s, int32_t, H1_4, DO_SQADD_S, DO_SQSUB_S)
DO_CADD(sve2_sqcadd_d, int64_t, , do_sqadd_d, do_sqsub_d)
#undef DO_CADD
#define DO_ZZI_SHLL(NAME, TYPEW, TYPEN, HW, HN) \
void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \
{ \

31
target/arm/translate-sve.c
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@ -6285,3 +6285,34 @@ static bool trans_BGRP(DisasContext *s, arg_rrr_esz *a)
}
return do_sve2_zzw_ool(s, a, fns[a->esz], 0);
}
static bool do_cadd(DisasContext *s, arg_rrr_esz *a, bool sq, bool rot)
{
static gen_helper_gvec_3 * const fns[2][4] = {
{ gen_helper_sve2_cadd_b, gen_helper_sve2_cadd_h,
gen_helper_sve2_cadd_s, gen_helper_sve2_cadd_d },
{ gen_helper_sve2_sqcadd_b, gen_helper_sve2_sqcadd_h,
gen_helper_sve2_sqcadd_s, gen_helper_sve2_sqcadd_d },
};
return do_sve2_zzw_ool(s, a, fns[sq][a->esz], rot);
}
static bool trans_CADD_rot90(DisasContext *s, arg_rrr_esz *a)
{
return do_cadd(s, a, false, false);
}
static bool trans_CADD_rot270(DisasContext *s, arg_rrr_esz *a)
{
return do_cadd(s, a, false, true);
}
static bool trans_SQCADD_rot90(DisasContext *s, arg_rrr_esz *a)
{
return do_cadd(s, a, true, false);
}
static bool trans_SQCADD_rot270(DisasContext *s, arg_rrr_esz *a)
{
return do_cadd(s, a, true, true);
}