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hw/openrisc: Fix masking in openrisc_pic_cpu_handler()

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Consider the masking of PICSR and PICMR:

    ((cpu->env.picsr && (1 << i)) && (cpu->env.picmr && (1 << i)))

To correctly mask bits, we should use the bitwise AND "&" rather than
the logical AND "&&".  Also, the loop is not necessary for masking.
Simply use (cpu->env.picsr & cpu->env.picmr).

Signed-off-by: Xi Wang <xi.wang@gmail.com>
Acked-by: Jia Liu <proljc@gmail.com>
This commit is contained in:
Jia Liu 2013-08-21 09:23:10 +08:00
parent b6d9766ddf
commit ed396e2b2d
1 changed files with 5 additions and 8 deletions
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7
hw/openrisc/pic_cpu.c
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@ -26,7 +26,6 @@ static void openrisc_pic_cpu_handler(void *opaque, int irq, int level)
{
OpenRISCCPU *cpu = (OpenRISCCPU *)opaque;
CPUState *cs = CPU(cpu);
int i;
uint32_t irq_bit = 1 << irq;
if (irq > 31 || irq < 0) {
@ -39,13 +38,11 @@ static void openrisc_pic_cpu_handler(void *opaque, int irq, int level)
cpu->env.picsr &= ~irq_bit;
}
for (i = 0; i < 32; i++) {
if ((cpu->env.picsr && (1 << i)) && (cpu->env.picmr && (1 << i))) {
if (cpu->env.picsr & cpu->env.picmr) {
cpu_interrupt(cs, CPU_INTERRUPT_HARD);
} else {
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
cpu->env.picsr &= ~(1 << i);
}
cpu->env.picsr = 0;
}
}