ppc-7.0 queue :
* ISA v3.1 vector instruction fixes * Compilation fix regarding 'struct pt_regs' definition -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmI4HooACgkQUaNDx8/7 7KHwSQ//fHrIZzDXzH7D7VjobfTcGrArZ5nzxbOnCo9AZOR6yqZbpb7JFBUH57z/ dYI4rlUzEHJu9JWir/ShJR7rO3t47gZVxM41e8KChth374dRwOI/4IMcFHkhTDAQ ORvAd6G3e19CxiyRBPKNt3kkbQDyY7EEzL2KvH/5LsZ4jlzvr1VNIiWeXb01iXrw rGug3wYhwH0lpDcLLibpV8S9J23E0Fw2vwkIahROq0Yf4a6YF+yG1PwkW0vr3cTr OESG1JWmFe3dV+mJOcRdB731OsPpVRTGaJ1+a9yA/iBE1PXnmawCaHPRKTDjrQfy x6Kd3tYw4Czjp2pIdibbQ9H6RP6f4AebwPoenxIVa7PgXrchD+RuqTepdBzfi6Q3 uIPlRgMw+TpROjDS55Ow1Wabuog0Vb7xR7sHRhhpxLa21oHVtTaeiu0CBXkThybF VYF5dUnxUj5Q3H8gyNJ7rP0YDMs8IAMGFZXPOc9X85rk5A1lEGdLDVRLFED06XkB BHdbV0m5pWr7s3fe6RXJLF8vvxi7af206tsBllfZH+FJiSqdXRlKX/pMBScgRNXn PqiTKi1v+VwZw1p8glijJKh9htrQ7Dlzh+CUpWpqOYs1icQ1oMEjESO5h65GtINK KaoyBncjysOmTLXDPhf/HojgOLW1MyD66KjYchnIAVehWlphNac= =FTNV -----END PGP SIGNATURE----- Merge tag 'pull-ppc-20220321' of https://github.com/legoater/qemu into staging ppc-7.0 queue : * ISA v3.1 vector instruction fixes * Compilation fix regarding 'struct pt_regs' definition # gpg: Signature made Mon 21 Mar 2022 06:43:22 GMT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * tag 'pull-ppc-20220321' of https://github.com/legoater/qemu: target/ppc: Replicate Double->Single-Precision result target/ppc: Replicate double->int32 result for some vector insns ppc64: Avoid pt_regs struct definition Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
ecf1bbe322
@ -1,38 +0,0 @@
|
||||
/*
|
||||
* host-signal.h: signal info dependent on the host architecture
|
||||
*
|
||||
* Copyright (c) 2003-2005 Fabrice Bellard
|
||||
* Copyright (c) 2021 Linaro Limited
|
||||
*
|
||||
* This work is licensed under the terms of the GNU LGPL, version 2.1 or later.
|
||||
* See the COPYING file in the top-level directory.
|
||||
*/
|
||||
|
||||
#ifndef PPC_HOST_SIGNAL_H
|
||||
#define PPC_HOST_SIGNAL_H
|
||||
|
||||
/* The third argument to a SA_SIGINFO handler is ucontext_t. */
|
||||
typedef ucontext_t host_sigcontext;
|
||||
|
||||
static inline uintptr_t host_signal_pc(host_sigcontext *uc)
|
||||
{
|
||||
return uc->uc_mcontext.regs->nip;
|
||||
}
|
||||
|
||||
static inline void host_signal_set_pc(host_sigcontext *uc, uintptr_t pc)
|
||||
{
|
||||
uc->uc_mcontext.regs->nip = pc;
|
||||
}
|
||||
|
||||
static inline void *host_signal_mask(host_sigcontext *uc)
|
||||
{
|
||||
return &uc->uc_sigmask;
|
||||
}
|
||||
|
||||
static inline bool host_signal_write(siginfo_t *info, host_sigcontext *uc)
|
||||
{
|
||||
return uc->uc_mcontext.regs->trap != 0x400
|
||||
&& (uc->uc_mcontext.regs->dsisr & 0x02000000);
|
||||
}
|
||||
|
||||
#endif
|
||||
@ -1 +1,41 @@
|
||||
#include "../ppc/host-signal.h"
|
||||
/*
|
||||
* host-signal.h: signal info dependent on the host architecture
|
||||
*
|
||||
* Copyright (c) 2003-2005 Fabrice Bellard
|
||||
* Copyright (c) 2021 Linaro Limited
|
||||
*
|
||||
* This work is licensed under the terms of the GNU LGPL, version 2.1 or later.
|
||||
* See the COPYING file in the top-level directory.
|
||||
*/
|
||||
|
||||
#ifndef PPC_HOST_SIGNAL_H
|
||||
#define PPC_HOST_SIGNAL_H
|
||||
|
||||
/* Needed for PT_* constants */
|
||||
#include <asm/ptrace.h>
|
||||
|
||||
/* The third argument to a SA_SIGINFO handler is ucontext_t. */
|
||||
typedef ucontext_t host_sigcontext;
|
||||
|
||||
static inline uintptr_t host_signal_pc(host_sigcontext *uc)
|
||||
{
|
||||
return uc->uc_mcontext.gp_regs[PT_NIP];
|
||||
}
|
||||
|
||||
static inline void host_signal_set_pc(host_sigcontext *uc, uintptr_t pc)
|
||||
{
|
||||
uc->uc_mcontext.gp_regs[PT_NIP] = pc;
|
||||
}
|
||||
|
||||
static inline void *host_signal_mask(host_sigcontext *uc)
|
||||
{
|
||||
return &uc->uc_sigmask;
|
||||
}
|
||||
|
||||
static inline bool host_signal_write(siginfo_t *info, host_sigcontext *uc)
|
||||
{
|
||||
return uc->uc_mcontext.gp_regs[PT_TRAP] != 0x400
|
||||
&& (uc->uc_mcontext.gp_regs[PT_DSISR] & 0x02000000);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
@ -2691,11 +2691,35 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
|
||||
do_float_check_status(env, GETPC()); \
|
||||
}
|
||||
|
||||
VSX_CVT_FP_TO_FP(xscvdpsp, 1, float64, float32, VsrD(0), VsrW(0), 1)
|
||||
VSX_CVT_FP_TO_FP(xscvspdp, 1, float32, float64, VsrW(0), VsrD(0), 1)
|
||||
VSX_CVT_FP_TO_FP(xvcvdpsp, 2, float64, float32, VsrD(i), VsrW(2 * i), 0)
|
||||
VSX_CVT_FP_TO_FP(xvcvspdp, 2, float32, float64, VsrW(2 * i), VsrD(i), 0)
|
||||
|
||||
#define VSX_CVT_FP_TO_FP2(op, nels, stp, ttp, sfprf) \
|
||||
void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
|
||||
{ \
|
||||
ppc_vsr_t t = { }; \
|
||||
int i; \
|
||||
\
|
||||
for (i = 0; i < nels; i++) { \
|
||||
t.VsrW(2 * i) = stp##_to_##ttp(xb->VsrD(i), &env->fp_status); \
|
||||
if (unlikely(stp##_is_signaling_nan(xb->VsrD(i), \
|
||||
&env->fp_status))) { \
|
||||
float_invalid_op_vxsnan(env, GETPC()); \
|
||||
t.VsrW(2 * i) = ttp##_snan_to_qnan(t.VsrW(2 * i)); \
|
||||
} \
|
||||
if (sfprf) { \
|
||||
helper_compute_fprf_##ttp(env, t.VsrW(2 * i)); \
|
||||
} \
|
||||
t.VsrW(2 * i + 1) = t.VsrW(2 * i); \
|
||||
} \
|
||||
\
|
||||
*xt = t; \
|
||||
do_float_check_status(env, GETPC()); \
|
||||
}
|
||||
|
||||
VSX_CVT_FP_TO_FP2(xvcvdpsp, 2, float64, float32, 0)
|
||||
VSX_CVT_FP_TO_FP2(xscvdpsp, 1, float64, float32, 1)
|
||||
|
||||
/*
|
||||
* VSX_CVT_FP_TO_FP_VECTOR - VSX floating point/floating point conversion
|
||||
* op - instruction mnemonic
|
||||
@ -2891,22 +2915,55 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
|
||||
|
||||
VSX_CVT_FP_TO_INT(xscvdpsxds, 1, float64, int64, VsrD(0), VsrD(0), \
|
||||
0x8000000000000000ULL)
|
||||
VSX_CVT_FP_TO_INT(xscvdpsxws, 1, float64, int32, VsrD(0), VsrW(1), \
|
||||
0x80000000U)
|
||||
VSX_CVT_FP_TO_INT(xscvdpuxds, 1, float64, uint64, VsrD(0), VsrD(0), 0ULL)
|
||||
VSX_CVT_FP_TO_INT(xscvdpuxws, 1, float64, uint32, VsrD(0), VsrW(1), 0U)
|
||||
VSX_CVT_FP_TO_INT(xvcvdpsxds, 2, float64, int64, VsrD(i), VsrD(i), \
|
||||
0x8000000000000000ULL)
|
||||
VSX_CVT_FP_TO_INT(xvcvdpsxws, 2, float64, int32, VsrD(i), VsrW(2 * i), \
|
||||
0x80000000U)
|
||||
VSX_CVT_FP_TO_INT(xvcvdpuxds, 2, float64, uint64, VsrD(i), VsrD(i), 0ULL)
|
||||
VSX_CVT_FP_TO_INT(xvcvdpuxws, 2, float64, uint32, VsrD(i), VsrW(2 * i), 0U)
|
||||
VSX_CVT_FP_TO_INT(xvcvspsxds, 2, float32, int64, VsrW(2 * i), VsrD(i), \
|
||||
0x8000000000000000ULL)
|
||||
VSX_CVT_FP_TO_INT(xvcvspsxws, 4, float32, int32, VsrW(i), VsrW(i), 0x80000000U)
|
||||
VSX_CVT_FP_TO_INT(xvcvspuxds, 2, float32, uint64, VsrW(2 * i), VsrD(i), 0ULL)
|
||||
VSX_CVT_FP_TO_INT(xvcvspuxws, 4, float32, uint32, VsrW(i), VsrW(i), 0U)
|
||||
|
||||
/*
|
||||
* Likewise, except that the result is duplicated into both subwords.
|
||||
* Power ISA v3.1 has Programming Notes for these insns:
|
||||
* Previous versions of the architecture allowed the contents of
|
||||
* word 0 of the result register to be undefined. However, all
|
||||
* processors that support this instruction write the result into
|
||||
* words 0 and 1 (and words 2 and 3) of the result register, as
|
||||
* is required by this version of the architecture.
|
||||
*/
|
||||
#define VSX_CVT_FP_TO_INT2(op, nels, stp, ttp, rnan) \
|
||||
void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
|
||||
{ \
|
||||
int all_flags = env->fp_status.float_exception_flags, flags; \
|
||||
ppc_vsr_t t = { }; \
|
||||
int i; \
|
||||
\
|
||||
for (i = 0; i < nels; i++) { \
|
||||
env->fp_status.float_exception_flags = 0; \
|
||||
t.VsrW(2 * i) = stp##_to_##ttp##_round_to_zero(xb->VsrD(i), \
|
||||
&env->fp_status); \
|
||||
flags = env->fp_status.float_exception_flags; \
|
||||
if (unlikely(flags & float_flag_invalid)) { \
|
||||
t.VsrW(2 * i) = float_invalid_cvt(env, flags, t.VsrW(2 * i), \
|
||||
rnan, 0, GETPC()); \
|
||||
} \
|
||||
t.VsrW(2 * i + 1) = t.VsrW(2 * i); \
|
||||
all_flags |= flags; \
|
||||
} \
|
||||
\
|
||||
*xt = t; \
|
||||
env->fp_status.float_exception_flags = all_flags; \
|
||||
do_float_check_status(env, GETPC()); \
|
||||
}
|
||||
|
||||
VSX_CVT_FP_TO_INT2(xscvdpsxws, 1, float64, int32, 0x80000000U)
|
||||
VSX_CVT_FP_TO_INT2(xscvdpuxws, 1, float64, uint32, 0U)
|
||||
VSX_CVT_FP_TO_INT2(xvcvdpsxws, 2, float64, int32, 0x80000000U)
|
||||
VSX_CVT_FP_TO_INT2(xvcvdpuxws, 2, float64, uint32, 0U)
|
||||
|
||||
/*
|
||||
* VSX_CVT_FP_TO_INT_VECTOR - VSX floating point to integer conversion
|
||||
* op - instruction mnemonic
|
||||
@ -2980,11 +3037,27 @@ VSX_CVT_INT_TO_FP(xvcvsxddp, 2, int64, float64, VsrD(i), VsrD(i), 0, 0)
|
||||
VSX_CVT_INT_TO_FP(xvcvuxddp, 2, uint64, float64, VsrD(i), VsrD(i), 0, 0)
|
||||
VSX_CVT_INT_TO_FP(xvcvsxwdp, 2, int32, float64, VsrW(2 * i), VsrD(i), 0, 0)
|
||||
VSX_CVT_INT_TO_FP(xvcvuxwdp, 2, uint64, float64, VsrW(2 * i), VsrD(i), 0, 0)
|
||||
VSX_CVT_INT_TO_FP(xvcvsxdsp, 2, int64, float32, VsrD(i), VsrW(2 * i), 0, 0)
|
||||
VSX_CVT_INT_TO_FP(xvcvuxdsp, 2, uint64, float32, VsrD(i), VsrW(2 * i), 0, 0)
|
||||
VSX_CVT_INT_TO_FP(xvcvsxwsp, 4, int32, float32, VsrW(i), VsrW(i), 0, 0)
|
||||
VSX_CVT_INT_TO_FP(xvcvuxwsp, 4, uint32, float32, VsrW(i), VsrW(i), 0, 0)
|
||||
|
||||
#define VSX_CVT_INT_TO_FP2(op, stp, ttp) \
|
||||
void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
|
||||
{ \
|
||||
ppc_vsr_t t = { }; \
|
||||
int i; \
|
||||
\
|
||||
for (i = 0; i < 2; i++) { \
|
||||
t.VsrW(2 * i) = stp##_to_##ttp(xb->VsrD(i), &env->fp_status); \
|
||||
t.VsrW(2 * i + 1) = t.VsrW(2 * i); \
|
||||
} \
|
||||
\
|
||||
*xt = t; \
|
||||
do_float_check_status(env, GETPC()); \
|
||||
}
|
||||
|
||||
VSX_CVT_INT_TO_FP2(xvcvsxdsp, int64, float32)
|
||||
VSX_CVT_INT_TO_FP2(xvcvuxdsp, uint64, float32)
|
||||
|
||||
/*
|
||||
* VSX_CVT_INT_TO_FP_VECTOR - VSX integer to floating point conversion
|
||||
* op - instruction mnemonic
|
||||
|
||||
Loading…
Reference in New Issue
Block a user