target-arm: A64: Add "Floating-point data-processing (2 source)" insns
This patch adds emulation for the "Floating-point data-processing (2 source)" group of instructions. Signed-off-by: Alexander Graf <agraf@suse.de> [WN: Commit message tweak, merge single and double precision patches. Rebase and update to new infrastructure. Incorporate FMIN/FMAX support patch by Michael Matz.] Signed-off-by: Will Newton <will.newton@linaro.org> [PMM: * added convenience accessors for FP s and d regs * pulled the field decode and opcode validity check up a level] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Alexander Graf
Peter Maydell
parent
f71a2ae50e
commit
ec73d2e096
@ -328,6 +328,60 @@ static inline int fp_reg_hi_offset(int regno)
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return offsetof(CPUARMState, vfp.regs[regno * 2 + 1]);
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}
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/* Convenience accessors for reading and writing single and double
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* FP registers. Writing clears the upper parts of the associated
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* 128 bit vector register, as required by the architecture.
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* Note that unlike the GP register accessors, the values returned
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* by the read functions must be manually freed.
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*/
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static TCGv_i64 read_fp_dreg(DisasContext *s, int reg)
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{
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TCGv_i64 v = tcg_temp_new_i64();
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tcg_gen_ld_i64(v, cpu_env, fp_reg_offset(reg, MO_64));
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return v;
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}
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static TCGv_i32 read_fp_sreg(DisasContext *s, int reg)
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{
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TCGv_i32 v = tcg_temp_new_i32();
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tcg_gen_ld_i32(v, cpu_env, fp_reg_offset(reg, MO_32));
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return v;
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}
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static void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v)
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{
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TCGv_i64 tcg_zero = tcg_const_i64(0);
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tcg_gen_st_i64(v, cpu_env, fp_reg_offset(reg, MO_64));
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tcg_gen_st_i64(tcg_zero, cpu_env, fp_reg_hi_offset(reg));
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tcg_temp_free_i64(tcg_zero);
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}
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static void write_fp_sreg(DisasContext *s, int reg, TCGv_i32 v)
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{
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TCGv_i64 tmp = tcg_temp_new_i64();
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tcg_gen_extu_i32_i64(tmp, v);
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write_fp_dreg(s, reg, tmp);
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tcg_temp_free_i64(tmp);
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}
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static TCGv_ptr get_fpstatus_ptr(void)
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{
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TCGv_ptr statusptr = tcg_temp_new_ptr();
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int offset;
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/* In A64 all instructions (both FP and Neon) use the FPCR;
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* there is no equivalent of the A32 Neon "standard FPSCR value"
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* and all operations use vfp.fp_status.
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*/
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offset = offsetof(CPUARMState, vfp.fp_status);
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tcg_gen_addi_ptr(statusptr, cpu_env, offset);
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return statusptr;
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}
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/* Set ZF and NF based on a 64 bit result. This is alas fiddlier
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* than the 32 bit equivalent.
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*/
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@ -3176,6 +3230,112 @@ static void disas_fp_1src(DisasContext *s, uint32_t insn)
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unsupported_encoding(s, insn);
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}
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/* C3.6.26 Floating-point data-processing (2 source) - single precision */
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static void handle_fp_2src_single(DisasContext *s, int opcode,
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int rd, int rn, int rm)
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{
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TCGv_i32 tcg_op1;
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TCGv_i32 tcg_op2;
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TCGv_i32 tcg_res;
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TCGv_ptr fpst;
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tcg_res = tcg_temp_new_i32();
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fpst = get_fpstatus_ptr();
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tcg_op1 = read_fp_sreg(s, rn);
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tcg_op2 = read_fp_sreg(s, rm);
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switch (opcode) {
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case 0x0: /* FMUL */
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gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x1: /* FDIV */
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gen_helper_vfp_divs(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x2: /* FADD */
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gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x3: /* FSUB */
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gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x4: /* FMAX */
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gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x5: /* FMIN */
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gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x6: /* FMAXNM */
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gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x7: /* FMINNM */
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gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x8: /* FNMUL */
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gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst);
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gen_helper_vfp_negs(tcg_res, tcg_res);
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break;
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}
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write_fp_sreg(s, rd, tcg_res);
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tcg_temp_free_ptr(fpst);
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tcg_temp_free_i32(tcg_op1);
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tcg_temp_free_i32(tcg_op2);
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tcg_temp_free_i32(tcg_res);
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}
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/* C3.6.26 Floating-point data-processing (2 source) - double precision */
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static void handle_fp_2src_double(DisasContext *s, int opcode,
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int rd, int rn, int rm)
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{
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TCGv_i64 tcg_op1;
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TCGv_i64 tcg_op2;
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TCGv_i64 tcg_res;
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TCGv_ptr fpst;
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tcg_res = tcg_temp_new_i64();
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fpst = get_fpstatus_ptr();
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tcg_op1 = read_fp_dreg(s, rn);
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tcg_op2 = read_fp_dreg(s, rm);
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switch (opcode) {
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case 0x0: /* FMUL */
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gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x1: /* FDIV */
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gen_helper_vfp_divd(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x2: /* FADD */
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gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x3: /* FSUB */
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gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x4: /* FMAX */
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gen_helper_vfp_maxd(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x5: /* FMIN */
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gen_helper_vfp_mind(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x6: /* FMAXNM */
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gen_helper_vfp_maxnumd(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x7: /* FMINNM */
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gen_helper_vfp_minnumd(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x8: /* FNMUL */
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gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst);
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gen_helper_vfp_negd(tcg_res, tcg_res);
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break;
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}
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write_fp_dreg(s, rd, tcg_res);
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tcg_temp_free_ptr(fpst);
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tcg_temp_free_i64(tcg_op1);
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tcg_temp_free_i64(tcg_op2);
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tcg_temp_free_i64(tcg_res);
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}
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/* C3.6.26 Floating point data-processing (2 source)
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* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
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* +---+---+---+-----------+------+---+------+--------+-----+------+------+
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@ -3184,7 +3344,27 @@ static void disas_fp_1src(DisasContext *s, uint32_t insn)
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*/
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static void disas_fp_2src(DisasContext *s, uint32_t insn)
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{
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unsupported_encoding(s, insn);
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int type = extract32(insn, 22, 2);
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int rd = extract32(insn, 0, 5);
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int rn = extract32(insn, 5, 5);
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int rm = extract32(insn, 16, 5);
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int opcode = extract32(insn, 12, 4);
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if (opcode > 8) {
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unallocated_encoding(s);
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return;
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}
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switch (type) {
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case 0:
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handle_fp_2src_single(s, opcode, rd, rn, rm);
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break;
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case 1:
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handle_fp_2src_double(s, opcode, rd, rn, rm);
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break;
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default:
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unallocated_encoding(s);
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}
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}
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/* C3.6.27 Floating point data-processing (3 source)
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