target/arm: Implement SVE floating-point arithmetic (predicated)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180627043328.11531-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
8092c6a314
commit
ec3b87c28e
@ -720,6 +720,83 @@ DEF_HELPER_FLAGS_5(gvec_rsqrts_s, TCG_CALL_NO_RWG,
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DEF_HELPER_FLAGS_5(gvec_rsqrts_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fadd_h, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fadd_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fadd_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fsub_h, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fsub_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fsub_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fmul_h, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fmul_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fmul_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fdiv_h, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fdiv_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fdiv_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fmin_h, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fmin_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fmin_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fmax_h, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fmax_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fmax_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fminnum_h, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fminnum_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fminnum_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fmaxnum_h, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fmaxnum_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fmaxnum_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fabd_h, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fabd_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fabd_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fscalbn_h, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fscalbn_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fscalbn_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fmulx_h, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fmulx_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fmulx_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_scvt_hh, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_scvt_sh, TCG_CALL_NO_RWG,
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@ -684,6 +684,23 @@ FTSMUL 01100101 .. 0 ..... 000 011 ..... ..... @rd_rn_rm
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FRECPS 01100101 .. 0 ..... 000 110 ..... ..... @rd_rn_rm
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FRSQRTS 01100101 .. 0 ..... 000 111 ..... ..... @rd_rn_rm
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### SVE FP Arithmetic Predicated Group
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# SVE floating-point arithmetic (predicated)
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FADD_zpzz 01100101 .. 00 0000 100 ... ..... ..... @rdn_pg_rm
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FSUB_zpzz 01100101 .. 00 0001 100 ... ..... ..... @rdn_pg_rm
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FMUL_zpzz 01100101 .. 00 0010 100 ... ..... ..... @rdn_pg_rm
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FSUB_zpzz 01100101 .. 00 0011 100 ... ..... ..... @rdm_pg_rn # FSUBR
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FMAXNM_zpzz 01100101 .. 00 0100 100 ... ..... ..... @rdn_pg_rm
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FMINNM_zpzz 01100101 .. 00 0101 100 ... ..... ..... @rdn_pg_rm
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FMAX_zpzz 01100101 .. 00 0110 100 ... ..... ..... @rdn_pg_rm
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FMIN_zpzz 01100101 .. 00 0111 100 ... ..... ..... @rdn_pg_rm
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FABD 01100101 .. 00 1000 100 ... ..... ..... @rdn_pg_rm
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FSCALE 01100101 .. 00 1001 100 ... ..... ..... @rdn_pg_rm
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FMULX 01100101 .. 00 1010 100 ... ..... ..... @rdn_pg_rm
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FDIV 01100101 .. 00 1100 100 ... ..... ..... @rdm_pg_rn # FDIVR
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FDIV 01100101 .. 00 1101 100 ... ..... ..... @rdn_pg_rm
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### SVE FP Unary Operations Predicated Group
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# SVE integer convert to floating-point
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@ -2811,6 +2811,95 @@ uint32_t HELPER(sve_while)(void *vd, uint32_t count, uint32_t pred_desc)
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return predtest_ones(d, oprsz, esz_mask);
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}
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/* Fully general three-operand expander, controlled by a predicate,
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* With the extra float_status parameter.
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*/
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#define DO_ZPZZ_FP(NAME, TYPE, H, OP) \
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void HELPER(NAME)(void *vd, void *vn, void *vm, void *vg, \
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void *status, uint32_t desc) \
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{ \
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intptr_t i = simd_oprsz(desc); \
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uint64_t *g = vg; \
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do { \
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uint64_t pg = g[(i - 1) >> 6]; \
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do { \
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i -= sizeof(TYPE); \
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if (likely((pg >> (i & 63)) & 1)) { \
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TYPE nn = *(TYPE *)(vn + H(i)); \
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TYPE mm = *(TYPE *)(vm + H(i)); \
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*(TYPE *)(vd + H(i)) = OP(nn, mm, status); \
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} \
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} while (i & 63); \
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} while (i != 0); \
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}
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DO_ZPZZ_FP(sve_fadd_h, uint16_t, H1_2, float16_add)
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DO_ZPZZ_FP(sve_fadd_s, uint32_t, H1_4, float32_add)
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DO_ZPZZ_FP(sve_fadd_d, uint64_t, , float64_add)
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DO_ZPZZ_FP(sve_fsub_h, uint16_t, H1_2, float16_sub)
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DO_ZPZZ_FP(sve_fsub_s, uint32_t, H1_4, float32_sub)
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DO_ZPZZ_FP(sve_fsub_d, uint64_t, , float64_sub)
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DO_ZPZZ_FP(sve_fmul_h, uint16_t, H1_2, float16_mul)
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DO_ZPZZ_FP(sve_fmul_s, uint32_t, H1_4, float32_mul)
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DO_ZPZZ_FP(sve_fmul_d, uint64_t, , float64_mul)
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DO_ZPZZ_FP(sve_fdiv_h, uint16_t, H1_2, float16_div)
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DO_ZPZZ_FP(sve_fdiv_s, uint32_t, H1_4, float32_div)
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DO_ZPZZ_FP(sve_fdiv_d, uint64_t, , float64_div)
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DO_ZPZZ_FP(sve_fmin_h, uint16_t, H1_2, float16_min)
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DO_ZPZZ_FP(sve_fmin_s, uint32_t, H1_4, float32_min)
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DO_ZPZZ_FP(sve_fmin_d, uint64_t, , float64_min)
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DO_ZPZZ_FP(sve_fmax_h, uint16_t, H1_2, float16_max)
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DO_ZPZZ_FP(sve_fmax_s, uint32_t, H1_4, float32_max)
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DO_ZPZZ_FP(sve_fmax_d, uint64_t, , float64_max)
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DO_ZPZZ_FP(sve_fminnum_h, uint16_t, H1_2, float16_minnum)
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DO_ZPZZ_FP(sve_fminnum_s, uint32_t, H1_4, float32_minnum)
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DO_ZPZZ_FP(sve_fminnum_d, uint64_t, , float64_minnum)
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DO_ZPZZ_FP(sve_fmaxnum_h, uint16_t, H1_2, float16_maxnum)
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DO_ZPZZ_FP(sve_fmaxnum_s, uint32_t, H1_4, float32_maxnum)
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DO_ZPZZ_FP(sve_fmaxnum_d, uint64_t, , float64_maxnum)
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static inline float16 abd_h(float16 a, float16 b, float_status *s)
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{
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return float16_abs(float16_sub(a, b, s));
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}
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static inline float32 abd_s(float32 a, float32 b, float_status *s)
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{
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return float32_abs(float32_sub(a, b, s));
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}
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static inline float64 abd_d(float64 a, float64 b, float_status *s)
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{
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return float64_abs(float64_sub(a, b, s));
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}
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DO_ZPZZ_FP(sve_fabd_h, uint16_t, H1_2, abd_h)
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DO_ZPZZ_FP(sve_fabd_s, uint32_t, H1_4, abd_s)
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DO_ZPZZ_FP(sve_fabd_d, uint64_t, , abd_d)
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static inline float64 scalbn_d(float64 a, int64_t b, float_status *s)
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{
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int b_int = MIN(MAX(b, INT_MIN), INT_MAX);
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return float64_scalbn(a, b_int, s);
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}
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DO_ZPZZ_FP(sve_fscalbn_h, int16_t, H1_2, float16_scalbn)
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DO_ZPZZ_FP(sve_fscalbn_s, int32_t, H1_4, float32_scalbn)
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DO_ZPZZ_FP(sve_fscalbn_d, int64_t, , scalbn_d)
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DO_ZPZZ_FP(sve_fmulx_h, uint16_t, H1_2, helper_advsimd_mulxh)
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DO_ZPZZ_FP(sve_fmulx_s, uint32_t, H1_4, helper_vfp_mulxs)
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DO_ZPZZ_FP(sve_fmulx_d, uint64_t, , helper_vfp_mulxd)
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#undef DO_ZPZZ_FP
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/* Fully general two-operand expander, controlled by a predicate,
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* With the extra float_status parameter.
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*/
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@ -3425,6 +3425,52 @@ DO_FP3(FRSQRTS, rsqrts)
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#undef DO_FP3
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/*
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*** SVE Floating Point Arithmetic - Predicated Group
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*/
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static bool do_zpzz_fp(DisasContext *s, arg_rprr_esz *a,
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gen_helper_gvec_4_ptr *fn)
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{
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if (fn == NULL) {
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return false;
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}
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if (sve_access_check(s)) {
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unsigned vsz = vec_full_reg_size(s);
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TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_16);
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tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd),
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vec_full_reg_offset(s, a->rn),
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vec_full_reg_offset(s, a->rm),
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pred_full_reg_offset(s, a->pg),
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status, vsz, vsz, 0, fn);
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tcg_temp_free_ptr(status);
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}
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return true;
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}
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#define DO_FP3(NAME, name) \
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static bool trans_##NAME(DisasContext *s, arg_rprr_esz *a, uint32_t insn) \
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{ \
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static gen_helper_gvec_4_ptr * const fns[4] = { \
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NULL, gen_helper_sve_##name##_h, \
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gen_helper_sve_##name##_s, gen_helper_sve_##name##_d \
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}; \
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return do_zpzz_fp(s, a, fns[a->esz]); \
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}
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DO_FP3(FADD_zpzz, fadd)
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DO_FP3(FSUB_zpzz, fsub)
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DO_FP3(FMUL_zpzz, fmul)
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DO_FP3(FMIN_zpzz, fmin)
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DO_FP3(FMAX_zpzz, fmax)
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DO_FP3(FMINNM_zpzz, fminnum)
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DO_FP3(FMAXNM_zpzz, fmaxnum)
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DO_FP3(FABD, fabd)
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DO_FP3(FSCALE, fscalbn)
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DO_FP3(FDIV, fdiv)
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DO_FP3(FMULX, fmulx)
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#undef DO_FP3
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/*
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*** SVE Floating Point Unary Operations Predicated Group
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