mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

target/riscv: Encode the FS and VS on a normal way for tb flags

Browse Source 
Reuse the MSTATUS_FS and MSTATUS_VS for the tb flags positions is not a
normal way.

It will make it hard to change the tb flags layout. And even worse, if we
want to keep tb flags for a same extension togather without a hole.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230324143031.1093-4-zhiwei_liu@linux.alibaba.com>
[rth: Adjust trans_rvf.c.inc as well; use the typedef]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-4-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-4-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
LIU Zhiwei 2023-04-12 13:43:11 +02:00 committed by Alistair Francis
parent 42967f4073
commit ebd476488d
5 changed files with 32 additions and 36 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
target/riscv/cpu.h
View File

@ -631,18 +631,17 @@ void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
#define TB_FLAGS_PRIV_MMU_MASK 3
#define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2)
#define TB_FLAGS_MSTATUS_FS MSTATUS_FS
#define TB_FLAGS_MSTATUS_VS MSTATUS_VS
#include "exec/cpu-all.h"
FIELD(TB_FLAGS, MEM_IDX, 0, 3)
FIELD(TB_FLAGS, LMUL, 3, 3)
FIELD(TB_FLAGS, SEW, 6, 3)
/* Skip MSTATUS_VS (0x600) bits */
FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1)
FIELD(TB_FLAGS, VILL, 12, 1)
/* Skip MSTATUS_FS (0x6000) bits */
FIELD(TB_FLAGS, FS, 3, 2)
/* Vector flags */
FIELD(TB_FLAGS, VS, 5, 2)
FIELD(TB_FLAGS, LMUL, 7, 3)
FIELD(TB_FLAGS, SEW, 10, 3)
FIELD(TB_FLAGS, VL_EQ_VLMAX, 13, 1)
FIELD(TB_FLAGS, VILL, 14, 1)
/* Is a Hypervisor instruction load/store allowed? */
FIELD(TB_FLAGS, HLSX, 15, 1)
FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2)

11
target/riscv/cpu_helper.c
View File

@ -79,16 +79,17 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
}
#ifdef CONFIG_USER_ONLY
flags |= TB_FLAGS_MSTATUS_FS;
flags |= TB_FLAGS_MSTATUS_VS;
flags = FIELD_DP32(flags, TB_FLAGS, FS, EXT_STATUS_DIRTY);
flags = FIELD_DP32(flags, TB_FLAGS, VS, EXT_STATUS_DIRTY);
#else
flags |= cpu_mmu_index(env, 0);
if (riscv_cpu_fp_enabled(env)) {
flags |= env->mstatus & MSTATUS_FS;
flags = FIELD_DP32(flags, TB_FLAGS, FS,
get_field(env->mstatus, MSTATUS_FS));
}
if (riscv_cpu_vector_enabled(env)) {
flags |= env->mstatus & MSTATUS_VS;
flags = FIELD_DP32(flags, TB_FLAGS, VS,
get_field(env->mstatus, MSTATUS_VS));
}
if (riscv_has_ext(env, RVH)) {

2
target/riscv/insn_trans/trans_rvf.c.inc
View File

@ -19,7 +19,7 @@
*/
#define REQUIRE_FPU do {\
if (ctx->mstatus_fs == 0) \
if (ctx->mstatus_fs == EXT_STATUS_DISABLED) \
if (!ctx->cfg_ptr->ext_zfinx) \
return false; \
} while (0)

8
target/riscv/insn_trans/trans_rvv.c.inc
View File

@ -29,12 +29,12 @@ static inline bool is_overlapped(const int8_t astart, int8_t asize,
static bool require_rvv(DisasContext *s)
{
return s->mstatus_vs != 0;
return s->mstatus_vs != EXT_STATUS_DISABLED;
}
static bool require_rvf(DisasContext *s)
{
if (s->mstatus_fs == 0) {
if (s->mstatus_fs == EXT_STATUS_DISABLED) {
return false;
}
@ -52,7 +52,7 @@ static bool require_rvf(DisasContext *s)
static bool require_scale_rvf(DisasContext *s)
{
if (s->mstatus_fs == 0) {
if (s->mstatus_fs == EXT_STATUS_DISABLED) {
return false;
}
@ -70,7 +70,7 @@ static bool require_scale_rvf(DisasContext *s)
static bool require_scale_rvfmin(DisasContext *s)
{
if (s->mstatus_fs == 0) {
if (s->mstatus_fs == EXT_STATUS_DISABLED) {
return false;
}

32
target/riscv/translate.c
View File

@ -64,10 +64,10 @@ typedef struct DisasContext {
RISCVMXL xl;
uint32_t misa_ext;
uint32_t opcode;
uint32_t mstatus_fs;
uint32_t mstatus_vs;
uint32_t mstatus_hs_fs;
uint32_t mstatus_hs_vs;
RISCVExtStatus mstatus_fs;
RISCVExtStatus mstatus_vs;
RISCVExtStatus mstatus_hs_fs;
RISCVExtStatus mstatus_hs_vs;
uint32_t mem_idx;
/*
* Remember the rounding mode encoded in the previous fp instruction,
@ -601,8 +601,6 @@ static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs)
#ifndef CONFIG_USER_ONLY
/*
* The states of mstatus_fs are:
* 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
* We will have already diagnosed disabled state,
* and need to turn initial/clean into dirty.
*/
@ -614,9 +612,9 @@ static void mark_fs_dirty(DisasContext *ctx)
return;
}
if (ctx->mstatus_fs != MSTATUS_FS) {
if (ctx->mstatus_fs != EXT_STATUS_DIRTY) {
/* Remember the state change for the rest of the TB. */
ctx->mstatus_fs = MSTATUS_FS;
ctx->mstatus_fs = EXT_STATUS_DIRTY;
tmp = tcg_temp_new();
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
@ -624,9 +622,9 @@ static void mark_fs_dirty(DisasContext *ctx)
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
}
if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) {
if (ctx->virt_enabled && ctx->mstatus_hs_fs != EXT_STATUS_DIRTY) {
/* Remember the stage change for the rest of the TB. */
ctx->mstatus_hs_fs = MSTATUS_FS;
ctx->mstatus_hs_fs = EXT_STATUS_DIRTY;
tmp = tcg_temp_new();
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
@ -640,8 +638,6 @@ static inline void mark_fs_dirty(DisasContext *ctx) { }
#ifndef CONFIG_USER_ONLY
/*
* The states of mstatus_vs are:
* 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
* We will have already diagnosed disabled state,
* and need to turn initial/clean into dirty.
*/
@ -649,9 +645,9 @@ static void mark_vs_dirty(DisasContext *ctx)
{
TCGv tmp;
if (ctx->mstatus_vs != MSTATUS_VS) {
if (ctx->mstatus_vs != EXT_STATUS_DIRTY) {
/* Remember the state change for the rest of the TB. */
ctx->mstatus_vs = MSTATUS_VS;
ctx->mstatus_vs = EXT_STATUS_DIRTY;
tmp = tcg_temp_new();
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
@ -659,9 +655,9 @@ static void mark_vs_dirty(DisasContext *ctx)
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
}
if (ctx->virt_enabled && ctx->mstatus_hs_vs != MSTATUS_VS) {
if (ctx->virt_enabled && ctx->mstatus_hs_vs != EXT_STATUS_DIRTY) {
/* Remember the stage change for the rest of the TB. */
ctx->mstatus_hs_vs = MSTATUS_VS;
ctx->mstatus_hs_vs = EXT_STATUS_DIRTY;
tmp = tcg_temp_new();
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
@ -1168,8 +1164,8 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->pc_succ_insn = ctx->base.pc_first;
ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX);
ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS;
ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS;
ctx->mstatus_fs = FIELD_EX32(tb_flags, TB_FLAGS, FS);
ctx->mstatus_vs = FIELD_EX32(tb_flags, TB_FLAGS, VS);
ctx->priv_ver = env->priv_ver;
ctx->virt_enabled = FIELD_EX32(tb_flags, TB_FLAGS, VIRT_ENABLED);
ctx->misa_ext = env->misa_ext;