hw/arm/mps2-tz: Add new mps3-an547 board
Add support for the mps3-an547 board; this is an SSE-300 based FPGA image that runs on the MPS3. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210219144617.4782-43-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell
parent
9fe1ea1126
commit
eb09d533d8
146
hw/arm/mps2-tz.c
146
hw/arm/mps2-tz.c
@ -17,6 +17,7 @@
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* "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505
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* "mps2-an521" -- Dual Cortex-M33 as documented in Application Note AN521
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* "mps2-an524" -- Dual Cortex-M33 as documented in Application Note AN524
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* "mps2-an547" -- Single Cortex-M55 as documented in Application Note AN547
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*
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* Links to the TRM for the board itself and to the various Application
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* Notes which document the FPGA images can be found here:
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@ -30,6 +31,8 @@
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* https://developer.arm.com/documentation/dai0521/latest/
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* Application Note AN524:
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* https://developer.arm.com/documentation/dai0524/latest/
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* Application Note AN547:
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* https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/DAI0547B_SSE300_PLUS_U55_FPGA_for_mps3.pdf
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*
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* The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide
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* (ARM ECM0601256) for the details of some of the device layout:
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@ -37,6 +40,8 @@
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* Similarly, the AN521 and AN524 use the SSE-200, and the SSE-200 TRM defines
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* most of the device layout:
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* https://developer.arm.com/documentation/101104/latest/
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* and the AN547 uses the SSE-300, whose layout is in the SSE-300 TRM:
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* https://developer.arm.com/documentation/101773/latest/
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*/
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#include "qemu/osdep.h"
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@ -68,13 +73,14 @@
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#include "hw/qdev-clock.h"
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#include "qom/object.h"
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#define MPS2TZ_NUMIRQ_MAX 95
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#define MPS2TZ_RAM_MAX 4
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#define MPS2TZ_NUMIRQ_MAX 96
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#define MPS2TZ_RAM_MAX 5
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typedef enum MPS2TZFPGAType {
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FPGA_AN505,
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FPGA_AN521,
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FPGA_AN524,
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FPGA_AN547,
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} MPS2TZFPGAType;
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/*
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@ -153,6 +159,7 @@ struct MPS2TZMachineState {
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#define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505")
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#define TYPE_MPS2TZ_AN521_MACHINE MACHINE_TYPE_NAME("mps2-an521")
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#define TYPE_MPS3TZ_AN524_MACHINE MACHINE_TYPE_NAME("mps3-an524")
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#define TYPE_MPS3TZ_AN547_MACHINE MACHINE_TYPE_NAME("mps3-an547")
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OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE)
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@ -252,6 +259,49 @@ static const RAMInfo an524_raminfo[] = { {
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},
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};
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static const RAMInfo an547_raminfo[] = { {
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.name = "itcm",
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.base = 0x00000000,
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.size = 512 * KiB,
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.mpc = -1,
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.mrindex = 0,
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}, {
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.name = "sram",
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.base = 0x01000000,
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.size = 2 * MiB,
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.mpc = 0,
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.mrindex = 1,
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}, {
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.name = "dtcm",
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.base = 0x20000000,
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.size = 4 * 128 * KiB,
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.mpc = -1,
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.mrindex = 2,
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}, {
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.name = "sram 2",
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.base = 0x21000000,
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.size = 4 * MiB,
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.mpc = -1,
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.mrindex = 3,
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}, {
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/* We don't model QSPI flash yet; for now expose it as simple ROM */
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.name = "QSPI",
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.base = 0x28000000,
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.size = 8 * MiB,
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.mpc = 1,
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.mrindex = 4,
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.flags = IS_ROM,
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}, {
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.name = "DDR",
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.base = 0x60000000,
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.size = MPS3_DDR_SIZE,
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.mpc = 2,
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.mrindex = -1,
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}, {
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.name = NULL,
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},
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};
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static const RAMInfo *find_raminfo_for_mpc(MPS2TZMachineState *mms, int mpc)
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{
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MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
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@ -893,6 +943,55 @@ static void mps2tz_common_init(MachineState *machine)
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},
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};
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const PPCInfo an547_ppcs[] = { {
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.name = "apb_ppcexp0",
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.ports = {
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{ "ssram-mpc", make_mpc, &mms->mpc[0], 0x57000000, 0x1000 },
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{ "qspi-mpc", make_mpc, &mms->mpc[1], 0x57001000, 0x1000 },
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{ "ddr-mpc", make_mpc, &mms->mpc[2], 0x57002000, 0x1000 },
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},
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}, {
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.name = "apb_ppcexp1",
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.ports = {
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{ "i2c0", make_i2c, &mms->i2c[0], 0x49200000, 0x1000 },
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{ "i2c1", make_i2c, &mms->i2c[1], 0x49201000, 0x1000 },
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{ "spi0", make_spi, &mms->spi[0], 0x49202000, 0x1000, { 53 } },
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{ "spi1", make_spi, &mms->spi[1], 0x49203000, 0x1000, { 54 } },
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{ "spi2", make_spi, &mms->spi[2], 0x49204000, 0x1000, { 55 } },
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{ "i2c2", make_i2c, &mms->i2c[2], 0x49205000, 0x1000 },
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{ "i2c3", make_i2c, &mms->i2c[3], 0x49206000, 0x1000 },
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{ /* port 7 reserved */ },
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{ "i2c4", make_i2c, &mms->i2c[4], 0x49208000, 0x1000 },
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},
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}, {
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.name = "apb_ppcexp2",
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.ports = {
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{ "scc", make_scc, &mms->scc, 0x49300000, 0x1000 },
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{ "i2s-audio", make_unimp_dev, &mms->i2s_audio, 0x49301000, 0x1000 },
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{ "fpgaio", make_fpgaio, &mms->fpgaio, 0x49302000, 0x1000 },
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{ "uart0", make_uart, &mms->uart[0], 0x49303000, 0x1000, { 33, 34, 43 } },
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{ "uart1", make_uart, &mms->uart[1], 0x49304000, 0x1000, { 35, 36, 44 } },
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{ "uart2", make_uart, &mms->uart[2], 0x49305000, 0x1000, { 37, 38, 45 } },
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{ "uart3", make_uart, &mms->uart[3], 0x49306000, 0x1000, { 39, 40, 46 } },
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{ "uart4", make_uart, &mms->uart[4], 0x49307000, 0x1000, { 41, 42, 47 } },
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{ "uart5", make_uart, &mms->uart[5], 0x49308000, 0x1000, { 125, 126, 127 } },
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{ /* port 9 reserved */ },
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{ "clcd", make_unimp_dev, &mms->cldc, 0x4930a000, 0x1000 },
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{ "rtc", make_rtc, &mms->rtc, 0x4930b000, 0x1000 },
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},
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}, {
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.name = "ahb_ppcexp0",
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.ports = {
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{ "gpio0", make_unimp_dev, &mms->gpio[0], 0x41100000, 0x1000 },
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{ "gpio1", make_unimp_dev, &mms->gpio[1], 0x41101000, 0x1000 },
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{ "gpio2", make_unimp_dev, &mms->gpio[2], 0x41102000, 0x1000 },
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{ "gpio3", make_unimp_dev, &mms->gpio[3], 0x41103000, 0x1000 },
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{ "eth-usb", make_eth_usb, NULL, 0x41400000, 0x200000, { 49 } },
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},
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},
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};
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switch (mmc->fpga_type) {
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case FPGA_AN505:
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case FPGA_AN521:
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@ -903,6 +1002,10 @@ static void mps2tz_common_init(MachineState *machine)
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ppcs = an524_ppcs;
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num_ppcs = ARRAY_SIZE(an524_ppcs);
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break;
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case FPGA_AN547:
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ppcs = an547_ppcs;
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num_ppcs = ARRAY_SIZE(an547_ppcs);
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break;
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default:
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g_assert_not_reached();
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}
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@ -981,6 +1084,11 @@ static void mps2tz_common_init(MachineState *machine)
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create_unimplemented_device("FPGA NS PC", 0x48007000, 0x1000);
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if (mmc->fpga_type == FPGA_AN547) {
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create_unimplemented_device("U55 timing adapter 0", 0x48102000, 0x1000);
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create_unimplemented_device("U55 timing adapter 1", 0x48103000, 0x1000);
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}
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create_non_mpc_ram(mms);
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armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
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@ -1115,6 +1223,33 @@ static void mps3tz_an524_class_init(ObjectClass *oc, void *data)
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mps2tz_set_default_ram_info(mmc);
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}
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static void mps3tz_an547_class_init(ObjectClass *oc, void *data)
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{
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MachineClass *mc = MACHINE_CLASS(oc);
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MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc);
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mc->desc = "ARM MPS3 with AN547 FPGA image for Cortex-M55";
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mc->default_cpus = 1;
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mc->min_cpus = mc->default_cpus;
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mc->max_cpus = mc->default_cpus;
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mmc->fpga_type = FPGA_AN547;
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mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m55");
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mmc->scc_id = 0x41055470;
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mmc->sysclk_frq = 32 * 1000 * 1000; /* 32MHz */
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mmc->apb_periph_frq = 25 * 1000 * 1000; /* 25MHz */
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mmc->oscclk = an524_oscclk; /* same as AN524 */
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mmc->len_oscclk = ARRAY_SIZE(an524_oscclk);
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mmc->fpgaio_num_leds = 10;
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mmc->fpgaio_has_switches = true;
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mmc->fpgaio_has_dbgctrl = true;
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mmc->numirq = 96;
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mmc->uart_overflow_irq = 48;
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mmc->init_svtor = 0x00000000;
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mmc->raminfo = an547_raminfo;
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mmc->armsse_type = TYPE_SSE300;
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mps2tz_set_default_ram_info(mmc);
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}
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static const TypeInfo mps2tz_info = {
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.name = TYPE_MPS2TZ_MACHINE,
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.parent = TYPE_MACHINE,
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@ -1146,12 +1281,19 @@ static const TypeInfo mps3tz_an524_info = {
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.class_init = mps3tz_an524_class_init,
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};
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static const TypeInfo mps3tz_an547_info = {
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.name = TYPE_MPS3TZ_AN547_MACHINE,
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.parent = TYPE_MPS2TZ_MACHINE,
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.class_init = mps3tz_an547_class_init,
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};
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static void mps2tz_machine_init(void)
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{
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type_register_static(&mps2tz_info);
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type_register_static(&mps2tz_an505_info);
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type_register_static(&mps2tz_an521_info);
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type_register_static(&mps3tz_an524_info);
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type_register_static(&mps3tz_an547_info);
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}
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type_init(mps2tz_machine_init);
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